Combinatorial loop with AhbLite3Decoder about vexriscv

[Dolu1990]

Hi ^^
I pushed a fix which avoid the combinatorial loop in the dbus toAhbLite3Master

Got things to generate succesfuly using

import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba3.ahblite._
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}

class AHBTest() extends Component{
  //CPU configuration
  val cpuConfig = VexRiscvConfig(
    plugins = List(
      new IBusSimplePlugin(
        resetVector = 0x80000000l,
        cmdForkOnSecondStage = false,
        cmdForkPersistence = true,
        prediction = STATIC,
        catchAccessFault = false,
        compressedGen = false
      ),
      new DBusSimplePlugin(
        catchAddressMisaligned = false,
        catchAccessFault = false
      ),
      new StaticMemoryTranslatorPlugin(
        ioRange      = _(31 downto 28) === 0xF
      ),
      new DecoderSimplePlugin(
        catchIllegalInstruction = true
      ),
      new RegFilePlugin(
        regFileReadyKind = plugin.SYNC,
        zeroBoot = false
      ),
      new IntAluPlugin,
      new SrcPlugin(
        separatedAddSub = false,
        executeInsertion = true
      ),
      new FullBarrelShifterPlugin,
      new MulPlugin,
      new DivPlugin,
      new HazardSimplePlugin(
        bypassExecute           = true,
        bypassMemory            = true,
        bypassWriteBack         = true,
        bypassWriteBackBuffer   = true,
        pessimisticUseSrc       = false,
        pessimisticWriteRegFile = false,
        pessimisticAddressMatch = false
      ),
      new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
      new BranchPlugin(
        earlyBranch = false,
        catchAddressMisaligned = true
      ),
      new CsrPlugin(
        config = CsrPluginConfig(
          catchIllegalAccess = false,
          mvendorid      = null,
          marchid        = null,
          mimpid         = null,
          mhartid        = null,
          misaExtensionsInit = 66,
          misaAccess     = CsrAccess.NONE,
          mtvecAccess    = CsrAccess.NONE,
          mtvecInit      = 0x00000020l,
          mepcAccess     = CsrAccess.READ_WRITE,
          mscratchGen    = false,
          mcauseAccess   = CsrAccess.READ_ONLY,
          mbadaddrAccess = CsrAccess.READ_ONLY,
          mcycleAccess   = CsrAccess.NONE,
          minstretAccess = CsrAccess.NONE,
          ecallGen       = false,
          wfiGenAsWait   = false,
          ucycleAccess   = CsrAccess.NONE,
          uinstretAccess = CsrAccess.NONE
        )
      ),
      new YamlPlugin("cpu0.yaml")
    )
  )

  //CPU instanciation
  val cpu = new VexRiscv(cpuConfig)
  var ibus : AhbLite3 = null
  var dbus : AhbLite3 = null

  //Checkout plugins used to instanciate the CPU to connect them to the SoC
  for(plugin <- cpu.plugins) plugin match{
    case plugin : IBusSimplePlugin =>
      ibus = master(plugin.iBus.toAhbLite3Master().toAhbLite3())
    case plugin : DBusSimplePlugin =>
      dbus = (plugin.dBus.toAhbLite3Master(true).toAhbLite3())
    case plugin: DebugPlugin => plugin.debugClockDomain {
      val jtag = slave(new Jtag()).setName("jtag")
      jtag <> plugin.io.bus.fromJtag()
      in(plugin.debugClockDomain.reset)
    }
    case plugin : CsrPlugin => {
      plugin.timerInterrupt.toIo()
      plugin.externalInterrupt.toIo()
    }
    case _ =>
  }

  val ram = AhbLite3OnChipRam(AhbLite3Config(32, 32), 16 kB)

  val dbusdecoder = AhbLite3Decoder(
    master = dbus,
    slaves = List(
      ram.io.ahb -> (0x10000000, 16 kB)
    ))
}

object VexRiscvAhbLite3{
  def main(args: Array[String]) {
    SpinalVerilog(new AHBTest())
  }
}