Comments (6)
Hoo i didn't knew about it.
It would be interresting :D
Thanks for the links.
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Maybe VexRISCV should auto generate this? The pipeline can be very different with different configs?
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Yes right it could be autogenerated, as it can very much,
- Branch predication can be turned off
- Miss prediction penality can vary much
- MUL can be iterative or single cycle with late result
- Shifts register can be iterative isntead of single cycle
- ...
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@futaris Do you know if this configuration is compiled into gcc or can it be provided at runtime?
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I was coincidentally looking at this yesterday as well.
When you read the paper where the automata was introduced (in 2003), the performance improvement can be significant in some cases (~10%) but that's for super-scalar architectures with asymmetric pipelines.
Even with all the configuration options, the VexRiscv still has a very conventional pipeline. I wonder what kind of upside there might be to have a custom version for each major configuration?
It might be sufficient to just have a version with the 3-stage deep MUL and other high clock speed settings. If you're going to use the iterative shift or multiply operations (with huge performance drop), performance was clearly not a priority to begin with, and the potential upside for a custom automata will probably very low. (<1%?)
Tom
from vexriscv.
@mithro I think it's compile time only.
Best to look at what microblaze and openrisc do in gcc.
https://github.com/Xilinx/meta-xilinx/tree/master/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7
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