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License: Apache License 2.0
Framework to perform DUT vs ISS (Whisper) lockstep architectural checks
License: Apache License 2.0
Hi,
Thanks for open sourcing this awesome project. I was trying to get it to run with Ocelet with the command provided when I ran into an error.
DEBUG: Rule 'whisper' indicated that a canonical reproducible form can be obtained by modifying arguments shallow_since = "1661036707 -0500"
DEBUG: Repository whisper instantiated at:
/<hidden>/cosim-arch-checker/WORKSPACE:4:15: in <toplevel>
INFO: Analyzed target //:dpi (0 packages loaded, 0 targets configured).
INFO: Found 1 target...
ERROR: /<hidden>/cosim-arch-checker/cac/src/BUILD:18:11: Compiling cac/src/register.cxx failed: (Exit 1): gcc failed: error executing command /usr/bin/gcc -U_FORTIFY_SOURCE -fstack-protector -Wall -Wunused-but-set-parameter -Wno-free-nonheap-object -fno-omit-frame-pointer '-std=c++0x' -MD -MF ... (remaining 17 arguments skipped)
Use --sandbox_debug to see verbose messages from the sandbox and retain the sandbox build root for debugging
cac/src/register.cxx: In constructor 'RegisterSnapshot::RegisterSnapshot(threadT)':
cac/src/register.cxx:45:21: error: 'class std::unordered_map<short unsigned int, Register>' has no member named 'insert_or_assign'
45 | snapshotCol.insert_or_assign(supportStateId, reg);
| ^~~~~~~~~~~~~~~~
Target //:dpi failed to build
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 3.263s, Critical Path: 1.51s
INFO: 73 processes: 58 internal, 15 linux-sandbox.
FAILED: Build did NOT complete successfully
From a quick grep of the source code the function doesn't seem to be present. Could you fix this on your end? Thanks!
Hi,
I'm integrating cosim-arch-checker
with my TB to do cosim.
When I'm executing the dhrystone
test on my RISCV core I get the following mismatch.
<752> DutGprWr: [Hart=0, Reg=X14, Data=0x2e1]
<752> DutRetire: [Hart=0, InstrTag=0x0 (0,0), PC=0x800029ac, Opcode=0xb0002773]
<752> Whisper Step #358: [Hart=0, InstrTag=0x0, ChangeCount=1, PC=0x800029ac, Opcode=0xb0002773, csrrs x14, mcycle, x0]
<752> Whisper Step #358: [Hart=0, InstrTag=0x0, Resource=r, Addr=0xe, Data=0x166]
Register Mismatch
Step: 358
X14 DUT:[Data:00000000000002e1]
SIM:[Data:0000000000000166]
PC DUT:[Data:00000000800029ac]
SIM:[Data:00000000800029ac]
Error: Core Arch Checker Mismatc
I think that mismatch between mcycle
value of my RISCV core and the Whisper ISS causes this error.
How can I adjust mcycle
value of the Whisper ISS?
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