thesourcerer8 / altium2kicad

Altium to KiCad converter for PCB and schematics

altium2kicad

Altium to KiCad converter for PCB and schematics

System requirements: Perl Optionally: https://github.com/cbernardo/kicad_oce_vis or https://github.com/twlostow/step2wrl or FreeCAD

To convert your Altium project to KiCad:

This software is also provided as an online service: http://www2.futureware.at/KiCad/

To use it on your computer, install the git client (e.g. apt-get install git ) and download the software (e.g. git clone https://github.com/thesourcerer8/altium2kicad/ ) Go to the directory with your .PcbDoc and .SchDoc files and run:

• perl unpack.pl (it unpacks the .PcbDoc and .SchDoc files into subdirectores)
• If the Altium design contains 3D models in step format, run kicadd_oce_vis or step2wrl or FreeCAD to convert the files to wrl (with FreeCAD open and execute the macro step2wrl.FCMacro )
• perl convertschema.pl (it converts the schematics from the subdirectories to .sch and -cache.lib files)
• perl convertpcb.pl (it converts the PCB to .kicad_pcb files)

Due to the huge differences between Altium and KiCad, the weak fileformat documentation and the high complexity of the fileformats, this converter cannot guarantee the quality of the conversion. Please verify the output of the converter If this converter does not work for your files, feel free to provide your files and screenshots of how they do look like and how they should look like, and I will try to help.

Current limitations of this converter:

• Design Rule Check settings are not converted

Currently known Limitations of KiCad:

• Bezier curves for component symbols -> WONTFIX -> Workaround with linearization
• Multi-line Text Frames
• A GND symbol with multiple horizontal lines arranged as a triangle
• Individual colors for single objects like lines, ...
• Ellipse
• Round Rectangle
• Elliptical Arc
• Rigid-Flex
• Octagonal pads not supported
• Arcs with a larger line thickness than the radius from Altium designs break the the VRML export
• STEP(STP) file support -> Will be fixed in the future, intermediate Workaround: Conversion with stp2wrl or FreeCAD

User Success Stories:

• https://github.com/FPGAwars/icezum/wiki The Alhambra board was migrated to KiCad with this converter

altium2kicad's Issues

Empty modules and y coordinates < 0

In the converted layout I have been experimenting with ( from https://github.com/bq/zum/tree/master/zum-core ) , the converter does not seem to populate module
pad, fp_line, or fp_arc fields
only the
fp_text fields

Is there a way to either populate these parts of the module, or suppress the module output in the converted layout?

Additionally, the y coordinates begin in the -ve Y hemiplane; is there a way to for x and y coordinates >= 0 ?

Good work on the converter though; amazing stuff!!

Cheers,

Erich.

Undefined subroutine &main::Sphere

convertpcb.pl gives Undefined subroutine &main::Sphere called at /Users/jacobrosenthal/Downloads/altium2kicad/convertpcb.pl line 1930.

Im not super familiar with perl, but I figured out that was presumably supposed to be a user defined function that never got written. In case anyone else runs into it and doesnt care about the 3d output, just comment out the line.

https://github.com/thesourcerer8/altium2kicad/blob/master/convertpcb.pl#L1930

Uninitialized value

I tried this script tonight and get this:
Handling Sheet1-SchDoc/Root Entry/FileHeader.dat
Use of uninitialized value in multiplication () at ./convertschema.pl line 110.
Use of uninitialized value in multiplication () at ./convertschema.pl line 111.
Use of uninitialized value in multiplication () at ./convertschema.pl line 110.
Use of uninitialized value in multiplication () at ./convertschema.pl line 111.

I do not need the board, per se, but the schematics would be great. As it is, I get an incomplete schematic and a board outline and no traces.

In the code for convertschema.pl, it looks for imagemagick from a dos/windows directory structure:
my $searchimagemagick="\\Program Files\\ImageMagick-6.8.9-Q16\\";
Is this correct? Am I doing something wrong?

VIA's are not imported

I have imported a board with via's. These are not present in the Kicad file.

Data from other layers ends up in bottom copper layer

Thanks for this converter! Really useful stuff.

We have a bunch of medium complexity Altium projects (all open hardware) over at Sinara and I converted a few of them to kicad.

When e.g. taking Kasli I get the following on "B.Cu":

There are a few issues:

• A lot of the items that should end up on layers like "F.SilkS" end up as copies on "B.Cu"
• Pads don't seem to be there at all
• "F/B.Mask" is empty

When opening the PCB layout in kicad (recent master), I get:

11:17:54 AM: file '/home/rj/work/m-labs/sinara/ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli-PCBDOC.kicad_pcb', line 1: '=' expected.
11:17:54 AM: file '/home/rj/work/m-labs/sinara/ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli-PCBDOC.kicad_pcb', line 3: '=' expected.
...
11:17:55 AM: file '/home/rj/work/m-labs/sinara/ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli-PCBDOC.kicad_pcb', line 107304: '=' expected.
11:17:55 AM: file '/home/rj/work/m-labs/sinara/ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli-PCBDOC.kicad_pcb', line 111495: '=' expected.

Double quotes coming from Altium need escaping.

altium2kicad/convertschema.pl

Line 1218 in e044347

push @{$parts{$globalp}},"F $counter \"".($d{'TEXT'}||"")."\" V 1400 2000 60 0001 C CNN \"".($d{'NAME'}||"")."\"\n";

Document not converter, no .pro file to be found

I've uploaded all the documents that I could get, which was the .schdoc, the .pcbdoc, and the BOM for the project in an excel sheet, but when I unzipped the file after downloading, there was no .pro file to open. When I tried opening the .schdoc files with kicad, it opens, but only shows me the connections I've made, but not a single component. No ICs, resistors, capacitors, or even ground connections. Please help.

No .pro file after conversion

Hi.
I tried converting 2 projects, but in both cases there was no .pro file in the output zip..
in the conversion log i dont see any error's, only warnings.

Writing to control-PcbDoc/Root Entry/Polygons6/Data.dat.txt
Warning: Pourindex -1 out of the expected range (0 .. 100)
Warning: Pourindex -1 out of the expected range (0 .. 100)

Any idea what im doing wrong?

Regards...

Double quotes in fields need to be escaped

altium2kicad/convertschema.pl

Line 1177 in e044347

$value = $partparams{lc($paramname)} || $value;

the description of the footprint should not be printed on the silkscreen layer

I've imported a pcb with a transistor. This PcbDoc has a schematic coupled to it. After converting I see the text "NPN General Purpose Amplifier" on the silkscreen. This text is coming from the field "Description" from the section "Schematic Reference information" of the footprint.

arcs are only exported when my $annotate=1;

Hi All,
At work i design electronics with Altium designer. I just stumbled over Altium2Kicad. I've tried to convert a simple PCB with only 1 transistor. I noticed the arcs on the silkscreen were missing, but only when my $annotate=0; This patch solves this issue:

`
convertpcb.pl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/convertpcb.pl b/convertpcb.pl
index bd788f1..49fcf00 100755
--- a/convertpcb.pl
+++ b/convertpcb.pl
@@ -1117,7 +1117,7 @@ sub HandleArc($$$$) # $filename,$value,?,$data (%d,$data,$header,$line);
print OUT "#Arc#$_[3]: WARNING: width/2 exceeds radius*1.01 !\n" if($annotate);
$width=$r/2.0;
}

• print OUT " (gr_arc (start $x $y) (end $x1 $y1) (angle $angle) (layer $layer) (width $width))\n" if($annotate);

• print OUT " (gr_arc (start $x $y) (end $x1 $y1) (angle $angle) (layer $layer) (width $width))\n";
  #print OUT " (gr_text "1" (at $x1 $y1) (layer $layer))\n";
  #print OUT " (gr_text "2" (at $x2 $y2) (layer $layer))\n";

`

import a board with a transistor: not all elements are seen as the footprint

Hi All,

I've made an Altium file with an BC547 transistor. After conversion, I see 3 pads with holes, the designator (Q1), the 2 arcs and a line on the silkscreen, and the comment "NPN General Purpose Amplifier".
When I right-click, clarify selection, footprint Q1 on F.cu, and move, I see only the 3 pads and the comment move, the other elements stay at the same place.

On closer inspection, sub HandleArc($$$$) does not have the needed info. In the .PcbDoc, the arc is stored with the position relative from the 0 point of the board, not relative to the 0 point of the footprint.

Cheers,
Cedric

Do you have a way to unpack the altium's libs ?

What about convert altium's schlib and pcblib to kicad?

XMOS audio board schematic altium2kicad not working?

Hey guys, I am pretty new here, but I would like to ask you if you can help me with converting a schematic to KiCad as I am unable to manage that. This is the link to the zip file https://www.xmos.com/support/boards?product=18334&component=19663
Thank you in advance.

How to parse the Data.dat.txt of Pads6?

Hi~
I want to get some information about pads from Pads6, but it's format is unreadable and different from the Data of Components6, how can I parse the format as follow, which extract from Pads\Data.dat.txt

0202000000 A: 0131 010000000005000000047C267C300100000000AA000000010C00FFFFFFFF7700FFFFFFFF674F7702CEB78102AF9B0600BC9A0300AF9B0600BC9A0300AF9B0600BC9A03000000000002020200000000008056400000000000000000A08601000400A0860100400D0300400D030000000000409C0000000000010101010101010000000000000000000001000001000000409C00 00006F2B48E334C02044AE0AA4D7EC7AFCAC2473142206AE25499A6A9A9BB9AEAB8F00000000FFFFFF7FFFFFFF7F00000000

Thanks in advance.

Power port labels are not translated

In my Altium schematic, the original file uses labeled power ports for different powers

Unfortunately these are lost in the translation:

Also if you look to the lower right all the parametric fields in the information block are lost and just put the values from altium without lookup: e.g. =sheetnumber

However, AWESOMEwork. This is amazing.

Double quotes in value need escaping

altium2kicad/convertschema.pl

Line 1202 in e044347

my $value = $d{'TEXT'};

components off-grid

Avatar-Power-Test.zip

Hi, I'm finding that the import of the schematic is importing the components as off-grid by 10 units (100 unit grid). This causes the Gnd pins not to import. The reason may be due the hard-coded symbols in my schematic symbols. I am using kicad 5.0.0-rc2.
I have attached the original Altium files.
thanks,
Greg

no unpacked PcbDoc files found

Hello i have used online altium to kicad converter
I am getting the same file for .schdoc and .pcbdoc in converted zip file
below is the conversion log
please help i confused what is problem
version of altium file that need to be taken care or any version can be converted ?

Archive: db/249.zip
creating: db/249/test/
inflating: db/249/test/SMPS.SchDoc
inflating: db/249/test/SMPS.PcbDoc
Done.
No unpacked .PcbDoc documents found. Trying to unpack it:
Done.
There were no unpacked PcbDoc files found.

Double quotes coming from Altium need escaping.

altium2kicad/convertschema.pl

Line 498 in e044347

$dat.="F $f \"$d{'TEXT'}\" H ".($d{'LOCATION.X'}*$f)." ".($sheety-$d{'LOCATION.Y'}*$f)."\n";

gr_arc duplication in exported Edge.Cut layer

I am unsure if altium has a duplicate representation of the outline (Edge.Cut) arcs or if the converter simply outputs them twice, but my impression is that they are exported twice:

box:~/altiumStuff/altium2kicad$ cat bqZUM_Core_Rev.2.6-PcbDoc.kicad_pcb | grep "gr_arc" | grep "45" | grep "ge.Cu"
(gr_arc (start 52.29160 101.28300) (end 53.05980 102.05120) (angle -45) (layer Edge.Cuts) (width 0.254))
(gr_arc (start 52.33511 104.48300) (end 51.48155 103.62944) (angle -45) (layer Edge.Cuts) (width 0.254))
(gr_arc (start 52.33511 118.28300) (end 51.12800 118.28300) (angle -45) (layer Edge.Cuts) (width 0.254))
(gr_arc (start 52.29160 121.48300) (end 53.37800 121.48300) (angle -45) (layer Edge.Cuts) (width 0.254))
(gr_arc (start 52.29160 101.28300) (end 53.05980 102.05120) (angle -45) (layer Edge.Cuts) (width 0.254))
(gr_arc (start 52.33511 104.48300) (end 51.48155 103.62944) (angle -45) (layer Edge.Cuts) (width 0.254))
(gr_arc (start 52.33511 118.28300) (end 51.12800 118.28300) (angle -45) (layer Edge.Cuts) (width 0.254))
(gr_arc (start 52.29160 121.48300) (end 53.37800 121.48300) (angle -45) (layer Edge.Cuts) (width 0.254))

It seems pcbnew is clever enough to ignore the duplicates fwiw.

Converting from Protel design files

Can altium2kicad convert from Protel design files?

If not, is there another tool to convert from Protel?

Maybe an intermediate tool, that possibly altium2kicad can use?

Thanks, Brendan.

Problem with line segments, segment should be gr_line on F.Silk

The straight lines in the rounded rectange that is supposed to containg the chinese logo thing, they are written as segments, where they should not. I don't know how to fix this. I just traced the problem.

The problem is with line segments, segment should be gr_line on F.Silk. The line that is problematic is:

3866 #Tracks#528: 210C00FFFFFFFFFFFFFFFFFFFFAA486E036D9C21022A0299036D9C210294330100000000000000000006000301
3867   (segment (start 146.20039 -90.82320) (end 153.31239 -90.82320) (width 0.20000) (layer F.SilkS) (net 1))

If changing to

3867   (gr_line (start 146.20039 -90.82320) (end 153.31239 -90.82320) (width 0.20000) (layer F.SilkS))

it is editable as a line in pcbnew.

This was done with ef52d4b

Altium to kicad convert isue

hii
i tied to convert altium pcb file to kicad pcb file in online
TP.zip

but its not getting convert can u please help in that

webench export to Altium

I'm trying to convert a webench design into kicad. Webench (https;//webench.ti.com) is a Texas Instruments tool for power supplies and what not. They don't support exporting directly into kicad, but they do support Altium. What webench spits out doesn't follow what your code is looking for. I've never used Altium so I'm not sure what to expect for it's output. Webench generates a zip file with the following files:

~/Altium/2017-03-02_19-43-15$ll
total 760
-rw-rw-r-- 1 rhowlett rhowlett 31200 Aug 2 2013 UL_Import.PrjScr
-rw-rw-r-- 1 rhowlett rhowlett 263 Aug 2 2013 UL_Form.pas
-rw-rw-r-- 1 rhowlett rhowlett 983 Aug 2 2013 UL_Form.dfm
-rw-rw-r-- 1 rhowlett rhowlett 36096 Jan 29 2016 UL_Import.pas
-rw-rw-r-- 1 rhowlett rhowlett 3296 Apr 1 2016 readme.txt
-rw-rw-r-- 1 rhowlett rhowlett 37412 Mar 2 19:43 2017-03-02_19-43-15.txt
-rw-rw-r-- 1 rhowlett rhowlett 757 Mar 2 19:43 2017-03-02_19-43-15.prjdoc
-rw-rw-r-- 1 rhowlett rhowlett 77725 Mar 2 19:43 2017-03-02_19-43-151.schdoc
-rw-rw-r-- 1 rhowlett rhowlett 50280 Mar 2 19:43 0603.stp
-rw-rw-r-- 1 rhowlett rhowlett 404924 Mar 2 19:43 DR74.stp
-rw-rw-r-- 1 rhowlett rhowlett 50372 Mar 2 19:43 0402.stp

In the code, I see you are looking for a file called FileHeader.dat in a directory call Root Entry. It looks like you are stuffing the contents of that file into a var called $contents. Just for grins do you think it would be possible to add an example Altium design (sch and pcb) so I have something to step though the code with so I know exactly what should be in the dat file? I write a bit of perl so this shouldn't be too much of a challenge:)

The convertpcb.pl gets a bit further but generates no files, just an empty directory (I'm going to look at that next).

Description of internal structure of PCBDOC file

Hi,
Is there any documentation which describes how to read files inside PCBDOC. Many files are strings which are coded binary data and I don't know how to read each number. I can dive into code for altium2kicad converter, but maybe there is some official documentation provided by Altium (I wrote an email to their support but I'm waiting for an answer).
Anyone heard about this or have some documentation?

Flexible layers

Sorry not an issue but a general question which I did not know where to ask.

Does the code also takes into account the different materials for different layers? I have flexible layers connecting some small islands and the main board.

Thanks in advance

Schematics not converted

Hi
I am trying to convert the opalkelly breakout board altium designer files to kicad. The tools appears to have failed to convert the schematic files. I am attaching all the relevant documents.

Can you please take a look?
Thank you!

BRK7305.zip
altium2kicad.zip

STEP->VRML conversion

As an alternative to a full FreeCAD installation, I would recommend using a tool which I created recently while experimenting to create a new 3D plugin for kicad:

https://github.com/cbernardo/kicad_oce_vis

Like Tom's conversion tool, which you currently use, this uses OpenCADCADE / OCE but the model traversal is more sophisticated so that even complex STEP assemblies will be rendered correctly.

Partial conversion

Hi,
I was trying to get Kicad Files from altium projet of Microchip EVB-KSZ9477.
I downloaded the original project here:
http://ww1.microchip.com/downloads/en/DeviceDoc/EVB-KSZ9477%20Evaluation%20Board%20Design%20Files.zip

After conversion I get this:
https://drive.google.com/open?id=1XMWaF3YRaRD6LuXWeiYS21OmvSU5W1L8

I can't get any simbol converted. Booth schematics and PCB are empty (except route). If I look at PCB, i have a large PCB with no component showed over.

Thank you, Roberto

groundplanes are correctly imported as zones, but they are not filled

I have imported an Altium file with a groundplane. This is correctly imported as a zone, but I have to press "B" (fill all zones), to have the groundplane to be filled with copper

Wrong recordtype: 0400, expected 0100 at pos 0

I am attempting to convert an Altium design (schematic and pcb) and ran in an issue. Here are the steps I took:

1. unpacked schema and pcb using unpack.pl
2. converted step files to wrl using FreeCad
3. Ran convertschema.pl. Got no errors, but some warnings about elliptical arcs not being supported
4. Ran convertpcb.pl. This is where I got an error:

ERROR: Wrong recordtype: 0400, expected 0100 at pos 0.
This record type is really unknown. Please contact the developer to add it.

No more conversion from Circuitmaker ? ( it seems to start obfuscating internal structure)

Hi,
I have tried to convert file from Circuitmaker , but it ends up with:
"There were no unpacked PcbDoc files found."

Short look into files shows that it stops on code:
...
my @files=glob('"*/Root Entry/Board6/Data.dat"');
if(!scalar(@files))
{
....

This failes becasue the internal structure looks like this:

4096 lis 9 10:02 068B9422DBB241258BA2DE9A6BA1A6
64 lis 9 10:03 068B9422DBB241258BA2DE9A6BA1A6.dat
64 lis 9 10:03 068B9422DBB241258BA2DE9A6BA1A6.dat.bin
4096 lis 9 10:02 0A342FA35A2D4FCDB8D2187D411EBC
64 lis 9 10:03 0A342FA35A2D4FCDB8D2187D411EBC.dat
64 lis 9 10:03 0A342FA35A2D4FCDB8D2187D411EBC.dat.bin
4096 lis 9 10:02 0DB009C021D946C88F1B3A32DAE94B
64 lis 9 10:03 0DB009C021D946C88F1B3A32DAE94B.dat
64 lis 9 10:03 0DB009C021D946C88F1B3A32DAE94B.dat.bin
4096 lis 9 10:02 17DC1EE78CF64F22A78C16A208DE80
64 lis 9 10:03 17DC1EE78CF64F22A78C16A208DE80.dat
64 lis 9 10:03 17DC1EE78CF64F22A78C16A208DE80.dat.bin

Missing Pads in the PCB file.

Ran your script as instructed but it seems all the pads in the layout file are missing. Is this a known issue. Is there a step I need to follow thats not in the instructions before the new pcb file will match up?

Thanks for your help

Altium2kicad does not generate archives

Hello there,
I am using Windows 10, Kicad 5 and Altium 17. I have downloaded Pearl to run the scripts.
Is it possible to convert just the PCBDoc from Altium? Or do I need pcb and sch? I share my pcb.
I cant convert the file to kicad.
Thank you so much.
Regards.-

DPM7107.zip

Create a testsuite to prevent conversion regressions

Firstly, this project is pretty awesome! Sadly a huge amount of the most complicated FOSS hardware is in Altium format :-( The guys from Upverter seem to have attempted to do something similar with https://github.com/upverter/schematic-file-converter but they seem to have gotten distracted.

It would be good if you had a test suite which checked that all the simple conversions worked properly.

I'm happy to help you create some basic Altium designs which cover various features you want to test. Do you want to create a list of things?

With PCB designs, I was thinking you could get kicad to generate gerber files from your generated kicad_pcb file and then compare them to the gerb files that Altium produces?

convertschema hangs on OS X

convertschema hangs on OS X (10.11.5). I get the following output and nothing else.

$ ~/Sandbox/altium2kicad/convertschema.pl 
Handling TEST-PcbLib/Root Entry/FileHeader.dat

Is there something special that has to be done on OS X ?

ERROR: Wrong recordtype: 0600, expected 0100 at pos 0

I've attempted to conver the OpenVizsla 3.2 Altium design from https://github.com/openvizsla/ov_ftdi/tree/master/hardware but I get the following error message:

ERROR: Wrong recordtype: 0600, expected 0100 at pos 0. This record type is really unknown. Please contact the developer to add it.

This is not super critical for me, I just wanted to give this converter a try and see how the results look like. As it's an OSHW design, you can try debugging the conversion error, if you're interested. Thanks!

IO error opening converted kicad_pcb

Dear Sorcerer,
Your convertpcb.pl creates a kicad_pcb out of a Altium PcbDoc. But when trying to open it in Kicad an io-error is reported: Error loading board.
IO_ERROR: Maximum line length exceeded
from /tmp/buildd/kicad-0.20140622+bzr4027/common/richio.cpp : ReadLine() : line 183
I will FTP the PcbDoc File to You. Would be great, if You find some time to look at it.
Your work is appreciated very much. Thanks.

Pads conversion failure with PCBDoc from AD17, AD15. Simple test case.

I'm not sure if it's some setting that is an issue, but boards that I create in AD17.1 (or even testing with AD15) will fail during conversion of pads.

Boiling down the problem to its essence, this simple board (one component with just a single pad) and also this other one (one component with a single pad; and a separate free pad) shows the problem behavior.

There's clearly some kind of extended data stored with the pads list, which the current parsing is not handling well:

Handling` a2k-failure-case-1-PcbDoc/Root Entry/Board6/Data.dat
Writing to a2k-failure-case-1-PcbDoc/Root Entry/Board6/Data.dat.txt
[...]
Pads6...
Warning: This is a rounded rectangle pad, and those are currently not supported by KiCad. We convert them to rounded pads for now, please verify the PCB design afterwards. This can cause overlaps and production problems!
substr outside of string at /cygdrive/c/Users/Joseph/Dropbox/work/safecast/test-altium/altium2kicad-master/altium2kicad/convertpcb.pl line 98.
substr outside of string at /cygdrive/c/Users/Joseph/Dropbox/work/safecast/test-altium/altium2kicad-master/altium2kicad/convertpcb.pl line 1746.
Use of uninitialized value in string eq at /cygdrive/c/Users/Joseph/Dropbox/work/safecast/test-altium/altium2kicad-master/altium2kicad/convertpcb.pl line 1746.
substr outside of string at /cygdrive/c/Users/Joseph/Dropbox/work/safecast/test-altium/altium2kicad-master/altium2kicad/convertpcb.pl line 1791.
Use of uninitialized value in string ne at /cygdrive/c/Users/Joseph/Dropbox/work/safecast/test-altium/altium2kicad-master/altium2kicad/convertpcb.pl line 1791.
Writing to a2k-failure-case-1-PcbDoc/Root Entry/Components6/Data.dat.txt
Writing to a2k-failure-case-1-PcbDoc/Root Entry/Tracks6/Data.dat.txt
Writing to a2k-failure-case-1-PcbDoc/Root Entry/FileVersionInfo/Data.dat.txt
Texts6...

Handling a2k-failure-case-2-PcbDoc/Root Entry/Board6/Data.dat
Writing to a2k-failure-case-2-PcbDoc/Root Entry/Board6/Data.dat.txt
Writing to a2k-failure-case-2-PcbDoc/Root Entry/UniqueIDPrimitiveInformation/Data.dat.txt
[...]
Pads6...
Warning: This is a rounded rectangle pad, and those are currently not supported by KiCad. We convert them to rounded pads for now, please verify the PCB design afterwards. This can cause overlaps and production problems!
Parsing error in Pads, header code 02 does not match 05 at pos 205 (0xCD)
Writing to a2k-failure-case-2-PcbDoc/Root Entry/Components6/Data.dat.txt
Writing to a2k-failure-case-2-PcbDoc/Root Entry/Tracks6/Data.dat.txt
Writing to a2k-failure-case-2-PcbDoc/Root Entry/FileVersionInfo/Data.dat.txt
Texts6...
`

Failed with "PARSE_ERROR: Un-terminated delimited string in input/source"

Might be a useful test case, given it's complexity, real-world-ness, and open source-ness:

https://github.com/TheThingsProducts/gateway/tree/develop/hardware

I used the online altium2kicad service, which succeeded, but opening the resulting kicad_pcb file resulted in the error:

PARSE_ERROR: Un-terminated delimited string in input/source

Turns out they were all to do with lines that contained net names like "\M\C\L\R\". I simply removed the last backslash from each of them and the pcb opened fine.

Full conversion log attached. All the "Seems we should skip 0x1e0 bytes" lines might be interesting too.
altium2kicad-conversionlog.txt

README would benefit from a screenshot

A picture is worth a thousand words. It would be awesome to have a picture in the README showing a design in Altium and KiCad side by side.

Database formats

Hello, I was wondering if you know the compatible Altium database formats for the converter? I have an older version of Altium (6.9) from which we would like to convert some files to Kicad.

I used the converter to convert the schematics. There was a problem with the grid. I determined that Kicad requires a 50mil grid and many of the components and wires imported were off grid.

I ran the convertpcb.pl script but I have been unable to get the pcb converted. When I run the script I see quite a few errors. I have attached some snips of the errors I noticed below.

Parsing error in Pads, header code 02 does not match 6A at pos 204

The following block of errors repeats several times:

Use of uninitialized value $aty in subtraction (-) at /altium2kicad/convertpcb.pl line 1728.
Use of uninitialized value $id in hash element at /altium2kicad/convertpcb.pl line 1733.
Use of uninitialized value $d{"MODELID"} in hash element at /altium2kicad/convertpcb.pl line 1749.
Use of uninitialized value in split at /altium2kicad/convertpcb.pl line 1755.
Use of uninitialized value $d{"MODEL.3D.ROTX"} in subtraction (-) at /altium2kicad/convertpcb.pl line 1758.
Use of uninitialized value $d{"MODEL.3D.ROTY"} in subtraction (-) at /altium2kicad/convertpcb.pl line 1758.
Use of uninitialized value $d{"MODEL.3D.ROTZ"} in subtraction (-) at /altium2kicad/convertpcb.pl line 1758.
Use of uninitialized value $id in hash element at /altium2kicad/convertpcb.pl line 1761.
Use of uninitialized value $id in hash element at /altium2kicad/convertpcb.pl line 1767.

There is one warning as well:

Warning: Pourindex -1 out of the expected range (0 .. 100)

And this is the last line:

Texts6...

I suspect my issue(s) maybe related to the vintage of my Altium files.

feature request: convert footprint to kicad

Hi,
following this thread:
https://forum.kicad.info/t/importing-a-samtec-footprint/10189/6
I'm wondering if you may consider to add the ability to convert also footprints to kicad format.
Many manufacturers may offer their product's footprint in this format.

This is a feature request, more than an issue, so feel free to close it.

Thx in advance
Maurice

Error loading board. IO_ERROR: Maximum line length exceeded from richio.cpp : ReadLine() : line 235

Hi,
I have converted a altium design file to kicad using altium2kikcad by following the video .When I tried to open the converted board file I got "Error loading board. IO_ERROR: Maximum line length exceeded from richio.cpp : ReadLine() : line 235". I found a discussion related to this error. In this link, the suggested solution is to remove the unnecessary data to make long lines shorter in kicad_pcb file. My file(Please find the attached file) has 27223 and I have no idea which lines to make shorter. Please help me in this regard.
board.zip

Thank You.

Error loading schematic file

I'm getting a "error loading schematic in file" on a converted file. .... expected single character token in input/source at line 965, offset7

After converting Altium sch file to kicad using atlium2kicad. I've tried to open the file and get this error:
I'm getting a "error loading schematic in file" on a converted file. .... expected single character token in input/source at line 965, offset7

kicad version 5.0.0 on windows. I'm running windows 10.

I believe the offending lines are:

$Comp
L CAP C1
U 1 1 5B82A5A6
P 13300 8900
F 0 "C1" H 13500 8820 60 0000 L BNN
F 1 "="Part Value"" H 13500 8730 60 0000 L BNN
F 2 "" H 13500 8730 60 0000 C CNN
F 3 "" H 13500 8730 60 0000 C CNN
1 13300 8900
1 0 0 -1
$EndComp

where line 965 is :
F 1 "="Part Value"" H 13500 8730 60 0000 L BNN

below is the cut and paste of the sch file

EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
EELAYER 27 0
EELAYER END
$Descr B 17000 11000
encoding utf-8
Sheet 1 1
Title "Sheet1-SOMconnectors-AB-SchDoc"
Date "26 08 2018"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
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P 1900 2100
F 0 "+5V" H 1900 2100 20 0000 C CNN
F 1 "++5V" H 1900 2030 30 0000 C CNN
F 2 "" H 1900 2100 70 0000 C CNN
F 3 "" H 1900 2100 70 0000 C CNN
1 1900 2100
1 0 0 -1
$EndComp
$Comp
L +5V #PWR?5B82A5BB
U 1 1 5B82A5BB
P 5400 2100
F 0 "+5V_2" H 5400 2100 20 0000 C CNN
F 1 "++5V" H 5400 2030 30 0000 C CNN
F 2 "" H 5400 2100 70 0000 C CNN
F 3 "" H 5400 2100 70 0000 C CNN
1 5400 2100
1 0 0 -1
$EndComp
$Comp
L +5V #PWR?5B82A5BA
U 1 1 5B82A5BA
P 9100 2100
F 0 "+5V_3" H 9100 2100 20 0000 C CNN
F 1 "++5V" H 9100 2030 30 0000 C CNN
F 2 "" H 9100 2100 70 0000 C CNN
F 3 "" H 9100 2100 70 0000 C CNN
1 9100 2100
1 0 0 -1
$EndComp
$Comp
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U 1 1 5B82A5B9
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F 0 "+5V_4" H 12600 2100 20 0000 C CNN
F 1 "++5V" H 12600 2030 30 0000 C CNN
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F 3 "" H 12600 2100 70 0000 C CNN
1 12600 2100
1 0 0 -1
$EndComp
$Comp
L GND #PWR?5B82A5B8
U 1 1 5B82A5B8
P 9200 7800
F 0 "GND" H 9200 7940 20 0000 C CNN
F 1 "+GND" H 9200 7910 30 0000 C CNN
F 2 "" H 9200 7800 70 0000 C CNN
F 3 "" H 9200 7800 70 0000 C CNN
1 9200 7800
1 0 0 -1
$EndComp
$Comp
L GND #PWR?5B82A5B7
U 1 1 5B82A5B7
P 12500 7800
F 0 "GND_2" H 12500 7940 20 0000 C CNN
F 1 "+GND" H 12500 7910 30 0000 C CNN
F 2 "" H 12500 7800 70 0000 C CNN
F 3 "" H 12500 7800 70 0000 C CNN
1 12500 7800
1 0 0 -1
$EndComp
$Comp
L GND #PWR?5B82A5B6
U 1 1 5B82A5B6
P 2000 7800
F 0 "GND_3" H 2000 7940 20 0000 C CNN
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F 3 "" H 2000 7800 70 0000 C CNN
1 2000 7800
1 0 0 -1
$EndComp
$Comp
L GND #PWR?5B82A5B5
U 1 1 5B82A5B5
P 5300 7800
F 0 "GND_4" H 5300 7940 20 0000 C CNN
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F 3 "" H 5300 7800 70 0000 C CNN
1 5300 7800
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$EndComp
Text Label 2700 8800 0 54 ~
ETH_COL
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ETH_CLK_OUT
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ETH_MDC
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ETH_CRS
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ETH_RST_N
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ETH_PWRDN_INT_N
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ETH_RX_CLK
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ETH_RX_D0
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ETH_RX_D1
Text Label 2700 9600 0 54 ~
ETH_RX_D2
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ETH_RX_D3
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ETH_RX_DV
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ETH_RX_ER
Text Label 2700 10000 0 54 ~
ETH_TX_CLK
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ETH_TX_D0
Text Label 2700 10200 0 54 ~
ETH_TX_D1
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ETH_TX_D2
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ETH_TX_D3
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ETH_TX_EN
Text HLabel 800 9500 2 60 BiDi ~
ETH_HARN
Text Label 2700 9100 0 54 ~
ETH_MDIO
Text Label 5700 3200 0 54 ~
ETH_COL
Text Label 900 4600 0 54 ~
ETH_CLK_OUT
Text Label 1100 3100 0 54 ~
ETH_MDC
Text Label 1100 4900 0 54 ~
ETH_CRS
Text Label 1100 5100 0 54 ~
ETH_RST_N
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ETH_PWRDN_INT_N
Text Label 1100 4500 0 54 ~
ETH_RX_CLK
Text Label 1100 3800 0 54 ~
ETH_RX_D0
Text Label 1100 3600 0 54 ~
ETH_RX_D2
Text Label 1100 3500 0 54 ~
ETH_RX_D3
Text Label 1100 3200 0 54 ~
ETH_RX_DV
Text Label 5700 3100 0 54 ~
ETH_RX_ER
Text Label 5600 4800 0 54 ~
ETH_TX_CLK
Text Label 5600 3500 0 54 ~
ETH_TX_D0
Text Label 5600 3600 0 54 ~
ETH_TX_D1
Text Label 5600 3800 0 54 ~
ETH_TX_D2
Text Label 5600 3900 0 54 ~
ETH_TX_D3
Text Label 1100 5200 0 54 ~
ETH_TX_EN
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ETH_MDIO
Text Label 5700 4100 0 54 ~
ETH_LINK
Text Label 1100 4100 0 54 ~
ETH_RX_D1
$Comp
L +3.3V #PWR?5B82A5B4
U 1 1 5B82A5B4
P 1700 2100
F 0 "+3.3V" H 1700 2100 20 0000 C CNN
F 1 "+3.3V" H 1700 2030 30 0000 C CNN
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F 3 "" H 1700 2100 70 0000 C CNN
1 1700 2100
1 0 0 -1
$EndComp
$Comp
L +3.3V #PWR?5B82A5B3
U 1 1 5B82A5B3
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F 0 "+3.3V_2" H 12800 2100 20 0000 C CNN
F 1 "+3.3V" H 12800 2030 30 0000 C CNN
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F 3 "" H 12800 2100 70 0000 C CNN
1 12800 2100
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$EndComp
$Comp
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F 3 "" H 5200 2100 70 0000 C CNN
1 5200 2100
1 0 0 -1
$EndComp
Text GLabel 6200 4100 2 60 Input ~
ETH_LINK
Text GLabel 600 7300 2 60 Input ~
MPU_INT
Text GLabel 5700 7100 2 60 Output ~
MPU_SCK
Text GLabel 600 7000 2 60 Input ~
MPU_SDO
Text GLabel 5700 6700 2 60 Output ~
MPU_SDI
Text GLabel 5700 7600 2 60 Output ~
MPU_CS
Text GLabel 600 7200 2 60 Output ~
MPU_FSYNC
Text GLabel 7900 7500 2 60 Input ~
CAN_RX1
Text GLabel 7900 7200 2 60 Output ~
CAN_TX1
Text GLabel 7900 5800 2 60 Output ~
UART_TX1
Text GLabel 7900 6400 2 60 Input ~
UART_RX1
Text GLabel 7900 6100 2 60 Output ~
UART_TX2
Text GLabel 7900 6900 2 60 Input ~
UART_RX2
Text GLabel 13500 3300 2 60 Input ~
CAN_RX2
Text GLabel 13500 3200 2 60 Output ~
CAN_TX2
Text GLabel 12800 7500 2 60 Input ~
UART_RX3
Text GLabel 12800 7200 2 60 Output ~
UART_TX4
Text GLabel 12800 7700 2 60 Input ~
UART_RX4
Text GLabel 12800 6900 2 60 Output ~
UART_TX3
$Comp
L +3.3V #PWR?5B82A5B1
U 1 1 5B82A5B1
P 8900 2100
F 0 "+3.3V_4" H 8900 2100 20 0000 C CNN
F 1 "+3.3V" H 8900 2030 30 0000 C CNN
F 2 "" H 8900 2100 70 0000 C CNN
F 3 "" H 8900 2100 70 0000 C CNN
1 8900 2100
1 0 0 -1
$EndComp
Text GLabel 600 6200 2 60 Output ~
BARO_SCK
Text GLabel 600 5600 2 60 Input ~
BARO_MISO
Text GLabel 600 5900 2 60 Output ~
BARO_MOSI
Text GLabel 5500 5600 2 60 Output ~
BARO_CS
Text Label 1100 2400 0 54 ~
JTAG_TDI
Text Label 5700 2400 0 54 ~
JTAG_TDO
Text Label 5800 9200 0 54 ~
JTAG_TDI
Text Label 5800 9100 0 54 ~
JTAG_TDO
$Comp
L +3.3V #PWR?5B82A5B0
U 1 1 5B82A5B0
P 4500 8800
F 0 "+3.3V_5" H 4500 8800 20 0000 C CNN
F 1 "+3.3V" H 4500 8730 30 0000 C CNN
F 2 "" H 4500 8800 70 0000 C CNN
F 3 "" H 4500 8800 70 0000 C CNN
1 4500 8800
1 0 0 -1
$EndComp
$Comp
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U 1 1 5B82A5AF
P 4500 9300
F 0 "GND_5" H 4500 9440 20 0000 C CNN
F 1 "+GND" H 4500 9410 30 0000 C CNN
F 2 "" H 4500 9300 70 0000 C CNN
F 3 "" H 4500 9300 70 0000 C CNN
1 4500 9300
1 0 0 -1
$EndComp
Text Label 5700 2300 0 54 ~
JTAG_TCK
Text Label 5800 9000 0 54 ~
JTAG_TCK
Text Label 1100 2300 0 54 ~
JTAG_TMS
Text Label 5800 8900 0 54 ~
JTAG_TMS
Text Label 8400 2800 0 54 ~
PG_1V8
Text Label 12900 2900 0 54 ~
PG_CARRIER
Text GLabel 7600 2800 2 60 Output ~
PG_1V8
Text GLabel 13500 2900 2 60 Input ~
PG_CARRIER
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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PG_5V
Text GLabel 6300 2500 2 60 Input ~
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FPGA_DONE
Text Label 8900 9800 0 54 ~
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$Comp
L GND #PWR?5B82A5AE
U 1 1 5B82A5AE
P 10100 10100
F 0 "GND_6" H 10100 10240 20 0000 C CNN
F 1 "+GND" H 10100 10210 30 0000 C CNN
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1 10100 10100
1 0 0 -1
$EndComp
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L GND #PWR?5B82A5AD
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$Comp
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$Comp
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$EndComp
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Text Label 6800 9800 0 54 ~
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11500 8800 11300 8800
Wire Wire Line
11300 9100 11300 8800
$Comp
L GND #PWR?5B82A5AA
U 1 1 5B82A5AA
P 11300 9100
F 0 "GND_8" H 11300 9240 20 0000 C CNN
F 1 "+GND" H 11300 9210 30 0000 C CNN
F 2 "" H 11300 9100 70 0000 C CNN
F 3 "" H 11300 9100 70 0000 C CNN
1 11300 9100
1 0 0 -1
$EndComp
$Comp
L GND #PWR?5B82A5A9
U 1 1 5B82A5A9
P 12900 9100
F 0 "GND_9" H 12900 9240 20 0000 C CNN
F 1 "+GND" H 12900 9210 30 0000 C CNN
F 2 "" H 12900 9100 70 0000 C CNN
F 3 "" H 12900 9100 70 0000 C CNN
1 12900 9100
1 0 0 -1
$EndComp
Wire Wire Line
12400 8600 12200 8600
Wire Wire Line
12400 8800 12400 8600
Wire Wire Line
12200 8800 12400 8800
Wire Wire Line
12900 8600 12400 8600
Wire Wire Line
12900 8700 12900 8600
Wire Wire Line
13400 8600 12900 8600
Wire Wire Line
13400 8800 13400 8600
$Comp
L GND #PWR?5B82A5A8
U 1 1 5B82A5A8
P 13400 9100
F 0 "GND_10" H 13400 9240 20 0000 C CNN
F 1 "+GND" H 13400 9210 30 0000 C CNN
F 2 "" H 13400 9100 70 0000 C CNN
F 3 "" H 13400 9100 70 0000 C CNN
1 13400 9100
1 0 0 -1
$EndComp
Wire Wire Line
700 2500 2200 2500
Text Label 700 2500 0 54 ~
CARRIER_SRSTn
Text Label 13000 8600 0 54 ~
CARRIER_SRSTn
Wire Wire Line
13800 8600 13400 8600
Wire Wire Line
1700 6500 2200 6500
Wire Wire Line
1700 6400 1700 6500
Wire Wire Line
1700 2100 1700 6400
Wire Wire Line
8900 6600 9400 6600
Wire Wire Line
8900 6500 8900 6600
Wire Wire Line
8900 2100 8900 6500
Connection ~ 1700 6400
Connection ~ 1900 5300
Connection ~ 2000 7400
Connection ~ 2000 6900
Connection ~ 2000 6100
Connection ~ 2000 5800
Connection ~ 2000 5000
Connection ~ 2000 4700
Connection ~ 2000 4300
Connection ~ 2000 4000
Connection ~ 2000 3700
Connection ~ 2000 3400
Connection ~ 4500 9200
Connection ~ 4500 8900
Connection ~ 5300 7400
Connection ~ 5300 6900
Connection ~ 5300 6400
Connection ~ 5300 5800
Connection ~ 5300 5000
Connection ~ 5300 4700
Connection ~ 5300 4300
Connection ~ 5300 4000
Connection ~ 5300 3700
Connection ~ 5300 3400
Connection ~ 5400 5300
Connection ~ 8900 6600
Connection ~ 8900 6500
Connection ~ 9100 5400
Connection ~ 9100 2900
Connection ~ 9200 7300
Connection ~ 9200 7000
Connection ~ 9200 6200
Connection ~ 9200 5900
Connection ~ 9200 5100
Connection ~ 9200 4800
Connection ~ 9200 4400
Connection ~ 9200 4100
Connection ~ 9200 3800
Connection ~ 9200 3500
Connection ~ 11300 8800
Connection ~ 12400 8600
Connection ~ 12500 7300
Connection ~ 12500 7000
Connection ~ 12500 6500
Connection ~ 12500 6200
Connection ~ 12500 5900
Connection ~ 12500 5100
Connection ~ 12500 4800
Connection ~ 12500 4400
Connection ~ 12500 4100
Connection ~ 12500 3800
Connection ~ 12500 3500
Connection ~ 12600 5400
Connection ~ 12900 8600
Connection ~ 13400 8600
$Comp
L Header_4X2 J5
U 1 1 5B82A5A7
P 4900 8800
F 0 "J5" H 4900 8800 60 0000 L BNN
F 1 "Header_4X2" H 4900 8210 60 0000 L BNN
F 2 "" H 4900 8210 60 0000 C CNN
F 3 "" H 4900 8210 60 0000 C CNN
1 4900 8800
1 0 0 -1
$EndComp
$Comp
L CAP C1
U 1 1 5B82A5A6
P 13300 8900
F 0 "C1" H 13500 8820 60 0000 L BNN
F 1 "="Part Value"" H 13500 8730 60 0000 L BNN
F 2 "" H 13500 8730 60 0000 C CNN
F 3 "" H 13500 8730 60 0000 C CNN
1 13300 8900
1 0 0 -1
$EndComp
$Comp
L PZSOM-JX1 PZSOM-JX1
U 1 1 5B82A5A5
P 2700 2100
F 0 "PZSOM-JX1" H 2700 2100 60 0000 L BNN
F 1 "="Part Number"" H 2700 -3700 60 0000 L BNN
F 2 "" H 2700 -3700 60 0000 C CNN
F 3 "" H 2700 -3700 60 0000 C CNN
1 2700 2100
1 0 0 -1
$EndComp
$Comp
L PZSOM-JX2 PZSOM-JX2
U 1 1 5B82A5A4
P 9900 2200
F 0 "PZSOM-JX2" H 9900 2200 60 0000 L BNN
F 1 "="Part Number"" H 9900 -3600 60 0000 L BNN
F 2 "" H 9900 -3600 60 0000 C CNN
F 3 "" H 9900 -3600 60 0000 C CNN
1 9900 2200
1 0 0 -1
$EndComp
$Comp
L NPN_0 IC4
U 1 1 5B82A5A3
P 7700 9700
F 1 "MMBT3904" H 7930 9530 60 0000 L BNN
F 2 "" H 7930 9530 60 0000 C CNN
F 3 "" H 7930 9530 60 0000 C CNN
1 7700 9700
1 0 0 -1
$EndComp
$Comp
L FET-N-3p IC5
U 1 1 5B82A5A2
P 9800 9500
F 1 "="Part Number"" H 10140 9330 60 0000 L BNN
F 2 "" H 10140 9330 60 0000 C CNN
F 3 "" H 10140 9330 60 0000 C CNN
1 9800 9500
1 0 0 -1
$EndComp
$Comp
L RES R5
U 1 1 5B82A5A1
P 7900 8800
F 0 "R5" V 7940 8760 60 0000 R TNN
F 1 "="Part Value"" V 7850 8760 60 0000 R TNN
F 2 "" H 7850 8760 60 0000 C CNN
F 3 "" H 7850 8760 60 0000 C CNN
1 7900 8800
0 -1 -1 0
$EndComp
$Comp
L RES R17
U 1 1 5B82A5A0
P 10100 8800
F 0 "R17" V 10140 8760 60 0000 R TNN
F 1 "="Part Value"" V 10050 8760 60 0000 R TNN
F 2 "" H 10050 8760 60 0000 C CNN
F 3 "" H 10050 8760 60 0000 C CNN
1 10100 8800
0 -1 -1 0
$EndComp
$Comp
L LED_C1-2p IC8
U 1 1 5B82A59F
P 8100 9100
F 1 "="Part Number"" V 8270 9100 60 0000 L BNN
F 2 "" H 8270 9100 60 0000 C CNN
F 3 "" H 8270 9100 60 0000 C CNN
1 8100 9100
0 1 1 0
$EndComp
$Comp
L LED_C1-2p IC9
U 1 1 5B82A59E
P 10300 9100
F 1 "="Part Number"" V 10470 9100 60 0000 L BNN
F 2 "" H 10470 9100 60 0000 C CNN
F 3 "" H 10470 9100 60 0000 C CNN
1 10300 9100
0 1 1 0
$EndComp
$Comp
L PB-SPST-4p IC10
U 1 1 5B82A59D
P 11600 8500
F 1 "="Part Number"" H 12100 8000 60 0000 R TNN
F 2 "" H 12100 8000 60 0000 C CNN
F 3 "" H 12100 8000 60 0000 C CNN
1 11600 8500
1 0 0 -1
$EndComp
$Comp
L RES R73
U 1 1 5B82A59C
P 12900 8900
F 0 "R73" V 12940 8860 60 0000 R TNN
F 1 "="Part Value"" V 12850 8860 60 0000 R TNN
F 2 "" H 12850 8860 60 0000 C CNN
F 3 "" H 12850 8860 60 0000 C CNN
1 12900 8900
0 -1 -1 0
$EndComp
$EndSCHEMATC

Failure to convert multiple sheet project

Hi @thesourcerer8 this is a great tool! I am trying to convert a complex Altium project and the output is nearly identical! This is a ten-layer board with ~300 components, so very impressive :)

One issue I have found is that it does not seem to work for multiple sheet hierarchies.

• Subsheets are not embedded
• Hierarchical labels are not imported

Here are some screenshots:

Altium:

KiCad:

Altium:

KiCad:

Altium:

KiCad:

Any thoughts or tips on how to approach this issue?

Error: Wrong recordtype: 0800, expected 0100

This record type is really unknown. Please contact the developer to add it.

worked well got kicad_pcb file that looks to be usable,
but no schematic at all.

Error loading PCB file

Hi,

First of all thanks for the great tool! I've generated a .kicad_pcb file from an Altium PCB using your online tool. In the log i cannot really see any error, but when i open the .kicad_pcb in KiCad i get the following error:

Error loading board.
PARSE_ERROR: Expecting "(" in input/source '3001510x-02_A_CC6UL_Starter_Board-PcbDoc.kicad_pcb'
line 8437
offset 41
from dsnlexer.cpp : Expecting() : line 361

Attached follows the .kicad_pcb as a .txt file. Any help is very welcome.

Thank you

3001510x-02_A_CC6UL_Starter_Board-PcbDoc.txt

Footprints without schematic designator are ignored

Hi All,
I've made a PcbDoc with a single footprint. There was no pcb project and no schematic. Altium2Kicad ignored this footprint. When I then double clicked the footprint in Altium, and types something in the Designator field under "Schematic Reference Information", the footprint was imported.

I think the convert script should have used the "Designator" field instead.