vhda / verilog_systemverilog.vim Goto Github PK

Is there any way of automatically testing folds or is it done manually at this point. If it's manual then I think I have a way of testing it automatically.

I was trying out your plugin (looks promising). I discovered that comments inside a module instantiation break indenting when there is a line that starts with a comment.

Example: The auto formatting indents the code as following:

`ifdef DO_THIS
    device d1 (
        .port (port[1]),
        // .port2(), comment
        .*
        );
    `endif

Should be:

`ifdef DO_THIS
    device d1 (
        .port (port[1]),
        // .port2(), comment
        .*
    );
`endif

However this formats correctly (comment is after port connection):

`ifdef DO_THIS
    device d1 (
        .port (port[1]),    // comment
        .*
    );
`endif

Other examples demonstrating the indent bug:

`ifdef DO_THIS
    device d1 (
        .port (port[1]),
        /* comment before port connection on the same line */ .port2()
        .*
        );
    `endif

`ifdef DO_THIS
    device2 d2 (
        .out,
        .a,
        .b(B)/*,
        TODO  .c(C) port not implemented yet */
        );
    `endif

Found an edge case that breaks the indentation script.

value = cond0         ? 0 :
        addr == 4'd14 ? a :
          cond1         ? b : 0;

Pretty sure it is the == causing the issue.

The Syntastic is a popular syntax checking plugin for Vim. This plugin is extensible and allow for other plugins to add their own parsers and/or syntax checkers, as is explained in their Syntax Checker Guide.

At the moment verilog_systemverilog.vim includes internally defined errorformat configurations for some Verilog/SystemVerilog compilers that can be selected through the VerilogErrorFormat function. Given the popularity to the above mentioned plugin it might make sense to consider supporting it directly for people who have it installed, while also keeping the current solution available for those who aren't.

This is a low priority issue that has the objective of opening a discussion to determine if this makes sense or not.

When g:verilog_syntax_fold is set to "block_named" and "block_nested" any word without a specific syntax defined for it is set to "verilogStatement" (same highlight as "begin" and "end").

This indents not as expected:

task run_phase(uvm_phase phase);

    assert(out>0)
        else $warning("xxx");
        $display("Hi");

    endtask

The following does not properly fold:

if (cond1) begin
    do1(); 
end else if (cond2) begin
    do2();
    do3();
    do4();
end else begin
    do5();
end

And further folds even worse:

if (cond1) 
    do1();
else if (cond2) begin
    do2();
    do3();
    do4();
end else begin
    do5();
end

More specifically; indenting doesn't work as desired if implementing from multiple interface classes and placing each interface on its own line. Example in question:

class a implements
    interface1, // Different indentation to following lines.
        interface2,
        interface3,
        interface4;

        function new(); // Wrong indentation
        endfunction
endclass

Preferably I would like the indentation to be as the following (if possible):

class a implements
        interface1,
        interface2,
        interface3,
        interface4;

    function new(); // Wrong indentation
    endfunction
endclass

Currently the indent script has no support for indenting code inside generate blocks.

I noticed that when stating a new line with # and smartindent is enabled, the line will un-indent back to column 0. Formatting with == or gg=V corrected the indenting, but the extra step is not desired.

Poking around the vim documentation I found this:

When typing '#' as the first character in a new line, the indent for that line is removed, the '#' is put in the first column. The indent is restored for the next line. If you don't want this, use this mapping: ":inoremap # X^H#", where ^H is entered with CTRL-V CTRL-H.

Adding au FileType verilog_systemverilog inoremap # X^H# to my ~/.vimrc is one solution. I am more in favor of add the below to indent/verilog_systemverilog.vim (or another file) so other users with smartindent will not run into the same issue.

" inoremap if smartindent is on (^H is CTRL-V CTRL-H)
inoremap # X^H#

From my tests, the change only effects the intended verilog/systemverilog files. c/cpp files retain the column shift functionality.

Note: don't copy-past inoremap # X^H#, the ^H need to entered as CTRL-V CTRL-H in vim

The following does not work:

class a;
    class b;
        //...
    endclass
endclass

Any idea on how this can be fixed?

This code indents incorrectly:

class x;
virtual function void pack(ref bit[W-1:0] out);
$display("hi");
endfunction
function void y();
endfunction
endclass

when removing the virtual keyword it is ok.

Current indent behaviour:

assign out = cond0 ? a :
             cond1 ? b :
             c;

Proposed indent behaviour:

assign out = cond0 ? a :
             cond1 ? b :
                     c ;

@vhda, what do you think about this.

@lewis6991, could you please confirm that what you wrote here is working as expected?

https://github.com/vhda/verilog_systemverilog.vim/blame/102f86f05ce30f19d6f0d068c73d2a58838f3d9d/README.md#L197-L207

I was reviewing the documentation and noticed that it is not working for me.

Thanks!

What should be:

module MyModule #(
  parameter A = 1,
  parameter B = 2
)(
  input I,
  output o
);

is indented as follows:

module MyModule #(
  parameter A = 1,
  parameter B = 2
  )(
    input I,
    output O
  );

And throws off all subsequent indentation. The same goes with instantiation:

MyModule #(
  .A (1),
  .B (2)
) Module_1 (
  .I (...),
  .O (...)
);

is indented as follows:

MyModule #(
  .A (1),
  .B (2)
  ) Module_1 (
    .I (...),
    .O (...)
  );

Reading a configuration variable may have some impact, even if small, on performance.

This issue serves as a reminder that this possible performance impact should be reviewed. The improvements should also take into account their impact on the user:

• Can the user dynamically update the configuration?
• Is it beneficial to have a local buffer override option together with a global version of the variable?

Items identified for review:

• Disable indent configuration (PR #94).

The following indents incorrectly:

task my_seq::body();

    `uvm_info({get_type_name(),"::body"}, "something" ,UVM_HIGH)
req = my_seq_item_REQ::type_id::create("req");

endtask

Review all variables in regards to consistency and functionality:

1. Decide if variable should be buffer local or global.
2. Decide if variable is still necessary.

Allow for breaking backward compatibility. Note: add warning to README.md.

Checklist (to be updated until release 3.0):

• Drop b:verilog_indent_modules
• Drop b:verilog_indent_preproc

Check vim7.3 compatibility.

thanks :)

Hello,

Currently it is possible to fold a number of constructs but as far as I know it is not possible to fold the text where verilog modules are being instantiated.

Would you consider this request?

Thanks anyway for the awesome plugin!

Because the indent script uses ); to determine indents, uvm macros don't indent properly.

For those who do not know, UVM is an infrastructure/library for SystemVerilog to provide a structured verification methodology. UVM uses `define macros heavily. For example the error reporting macro is:

`uvm_info("TAG", "message", UVM_MEDIUM)

The awkward thing about these macros is they do not require a ; at the end of them and some simulators actually provide warning if you do. Also in some cases providing the ; can cause an error:

if (condition)
  `uvm_info("TAG", "message1", UVM_MEDIUM);
else
  `uvm_info("TAG", "message2", UVM_NONE);

This will cause an error because the simulator will see ;; after the first if and will put the else out of context.

I understand that this is a complex issue so I accept that a solution to this may be infeasible.

Any solution would have to detect a ) and then check if it belongs to a macro or not.

It seems I can not get the correct indent when I use a struct typedef as below. It for example indents as:

class z;

typedef struct { 
    real a;
int b;             
int c;               
real d; } ts;
ts s[];

int unsigned cnt=0;

function new();
    super.new();
endfunction;

endclass;

It seems when {} is present in a comment, the next line wrongly indented:

task m;

    if(scope_name=="") begin
        scope_name = get_full_name();  // fdfds {dfsdfs}
end

endtask

I am hesitant to submit this issue as this pretty basic, and might be an error in my side.

module m (input clk);

import uvm_pkg::*;

initial begin
    $display("something");
end

endmodule

The content of the module does not seem to be indented?

Sorry for the n00b question, but I just realized that my .v files are still recognized as "verilog" files and not "verilog_systemverilog". Any reason why the default filetype file would take precedence ?

Looks to me like there a syntax error in the omni complete function. When I try to use omni, vim gives me the following error:

Error detected while processing function verilog_systemverilog#Complete:
line 119:
E583: multiple :else:   else

File used on:

class b;
   bit field1;
   bit field2;
endclass : b

class a;
    b b_inst;

    function void update();
        b_inst.[omni complete here]
    endfunction : update
endclass : a

class c;
    extern function f();
    extern function g();
    /*
    this is commented out
    this is commented out
    this is commented out
    */
   extern function h();
endclass

does not indent correctly.

this code:

task run_phase(uvm_phase phase);

    assert(out>0) else $warning("xxx");
    assert(out>0) else $warning("xxx");
foreach(out[i]) begin
    out[i]=new;
end


endtask

doesn't indent correctly.

With a single assert it does indent correctly

This does not indent correctly:

virtual class base;

    pure virtual function void a(input int unsigned N, ref t Data);
        pure virtual function void b(input int unsigned N, ref t Data);
            pure virtual function void c(input int unsigned N, ref t Data);

            endclass;

fork - join with named begin/end block indenting seems to be broken:

task run_phase(uvm_phase phase);

    fork 
    begin : isolating_thread
        do_something();
    end : isolating_thread 
join

endtask

Given the following example:

module top;
  function f(
    input a,
    input b
  );
  endfunction : f

  initial begin
    f(.<tab>
    );
  end
endmodule

When pressing inside the function port list will not work as expected. This happens because the qualified output of ctags is the following:

a       o.v     /^    input a,$/;"      p       function:top.f
b       o.v     /^    input b$/;"       p       function:top.f
f       o.v     /^  function f($/;"     f       module:top
top     o.v     /^module top;$/;"       m
top.f   o.v     /^  function f($/;"     f       module:top
top.f.a o.v     /^    input a,$/;"      p       function:top.f
top.f.b o.v     /^    input b$/;"       p       function:top.f

So f.a is only available in the context top.

For this reason the omni-completion script must determine the current context before searching for tags, such that it can search for top.f.* instead of f.*.

Syntax highlighting disappears for the following examples:

• 100ns
• 2_0ps
• 3_000_000s

This issue has the purpose of tracking any reported syntax performance issues.
New issues should be added as a comment and I will update the list accordingly.
Please provide example code whenever possible.

• Poor performance in when there is a fold that occupies the complete file - Vim limitation, can be overcome using FastFold plugin.
• Introduce new global variable to disable the slower syntax elements.
• Try to optimize performance of slower syntax elements, as reported in #42 (comment), below.

I'm trying to enable the verbose logging for the omni-completion script. Could someone tell me the flow for doing this? I'm fairly new to vimscript so assume I know nothing.

Thanks

This code does not indent as expected:

task run_phase(uvm_phase phase);

    assert(my_seq.randomize());
    my_seq.start(low_sequencer_h);

    assert(my_seq.randomize() with {Nr==6;});
my_seq.start(low_sequencer_h);

assert(my_seq.randomize() with 
{Nr==6; Time==8;});
my_seq.start(low_sequencer_h);

endtask

In the following situation:

case (Signal)
  2'd0: begin Result <= 0; end
  2'd1: begin Result <= 1; end
  2'd2: begin Result <= 2; end
  default: begin Result <= 0; end
endcase

the automatic indenting gives the result below:

case (Signal)
  2'd0: begin Result <= 0; end
    2'd1: begin Result <= 1; end
      2'd2: begin Result <= 2; end
        default: begin Result <= 0; end
endcase

function bit return_something();
    return a &
        b |
        c;
endfunction

Should be:

function bit return_something();
    return a &
           b |
           c;
endfunction

cover property (
    a &&
        b &&
        c
);

Update: This has been fixed from other changes.

The following if without begin/end stays indented for more than 1 line:

function void sink_driver::build_phase(uvm_phase phase);
if (!uvm_config_db #(sink_agent_config)::get(this, "", "sink_agent_config", m_cfg) )
`uvm_fatal("CONFIG_LOAD", "Cannot get() configuration sink_agent_config from uvm_config_db. Have you set() it?")
// OK to do this herE>
foreach(rand_bool_gen[ch]) begin
rand_bool_gen[ch]=new();
end
endfunction

Must support:

pure virtual { class_item_qualifier } method_prototype ;
extern { method_qualifier } method_prototype ;

class_item_qualifier ::=
  static
  | protected
  | local

method_qualifier ::=
  [ pure ] virtual
  | class_item_qualifier

If a comment line contains the 'if' keyword the next line of comments is indented:

// if there is...
// more comments

Current behaviour:

assert_label: assert property (  
    precondition |-> a &&
    b &&
    c
);

Proposed:

assert_label: assert property (  
    precondition |-> a &&
                     b &&
                     c
);

I've been using the following with NCVerilog and UVM and it works reasonably well. UVM_FATAL does highlight during the summary report at the end, but the rest seems good. I would suggest test-driving and adding these to your existing toolset options.

" From https://github.com/ryanlee/vim/blob/master/vimfiles/compiler/ncverilog.vim
set errorformat+=%A%p\|,%Z%.%#:\ \*%t\\,%.%#\ \(%f\\,%l\|%c\):%m
" Ignore warnings (keep a copy looking for %t instead of W to define errors as errors)
set errorformat+=%-G%.%#\ *W\\,%.%#(%f\\,%l\|%c):\ %m
" Add abillity to parse verilog errors (%t matches 'E' or 'W' for type):
set errorformat+=%.%#\ *%t\\,%.%#(%f\\,%l\|%c):\ %m
" Assertions don't have the column information:
set errorformat+=%.%#\ *%t\\,%.%#(%f\\,%l):\ %m
"set errorformat=%.%#\ *%t\\,%.%#(%f\\,%l):\ %m
" Add abillity to parse NULL pointer errors:
set errorformat+=%E%>%.%#\ *E\\,%m,%C%.%#File:\ %f\\,\ line\ =\ %l\\,\ pos\ =\ %c,%Z%m
" Add abillity to parse assertion errors %.%# is like .* in regex:
set errorformat+=%.%#:\ *%t\\,%.%#\ (%f\\,%l):\ %m
" Add abillity to parse UVM errors:
set errorformat+=UVM_%tRROR\ %f(%l)\ %m
set errorformat+=UVM_%tRROR:\ %m
set errorformat+=%-GUVM_ERROR\ :%p0
"UVM_FATAL is an error that has no file associate with it.
" If we add it to errorformat, we lose visibility of "UVM_FATAL"
" This is an issue with the simulation report...
set errorformat+=UVM_FATAL\ %f(%l)\ %m
set errorformat+=%-GUVM_FATAL\ :%p0
set errorformat+=UVM_FATAL\ %m
"Ignore tool version information 'ncvlog(64): version......'
set errorformat+=-G^ncelab(64):%.%#
set errorformat+=-G^ncvlog(64):%.%#
set errorformat+=-G^irun(64):%.%#
set errorformat-=%f(%l):%m "This is subtractive as it catches the tool name as an error

IEEE Std 1800-2005 missing keyword highlighting:

• unique

IEEE Std 1800-2009 missing keyword highlighting:

• accept_on
• eventually
• global
• implies
• let
• nexttime
• reject_on
• restrict
• s_always
• s_eventually
• s_nexttime
• s_until
• s_until_with
• strong
• sync_accept_on
• sync_reject_on
• unique0
• until
• until_with
• untyped
• weak

IEEE Std 1800-2012 missing keyword highlighting:

• implements
• interconnect
• nettype
• soft

Source : IEEE Std 1800-2012 § 22.14.6 IEEE 1800-2005 keywords, § 22.14.7 IEEE 1800-2009 keywords, & § 22.14.8 IEEE 1800-2012 keywords

The option b:verilog_indent_modules allows having the code indented inside modules, but there is no such option for class, interface, etc. There should exist a new option that allows this, preferably something that allows configuration of which elements to indent, like is done with g:verilog_syntax_fold.