xilinx / chaidnn Goto Github PK

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

License: Other

C 4.31% Makefile 0.09% Tcl 0.01% C++ 95.50% Objective-C 0.09% Shell 0.01% CMake 0.01%

dnn embedded-vision inference deep-neural-networks alexnet googlenet xilinx xilinx-ultrascale-mpsocs

chaidnn's Introduction

CHaiDNN-v2
Analysis and Eval
	Supported Layers		Performance/Resource Utilization

	Performance Eval



Design and Development
	API Reference	Quantization User Guide for CHaiDNN	Model Zoo	Running Inference on new Network

	Creating SDx GUI Project	Configurable Parameters	Custom Platform Generation	Software Layer Plugin

	SDSoC Environment User Guide		Hardware-Software Partitioning for Performance

Introduction

CHaiDNN is a Xilinx Deep Neural Network library for acceleration of deep neural networks on Xilinx UltraScale MPSoCs. It is designed for maximum compute efficiency at 6-bit integer data type. It also supports 8-bit integer data type.

The design goal of CHaiDNN is to achieve best accuracy with maximum performance. The inference on CHaiDNN works in fixed point domain for better performance. All the feature maps and trained parameters are converted from single precision to fixed point based on the precision parameters specified by the user. The precision parameters can vary a lot depending upon the network, datasets, or even across layers in the same network. Accuracy of a network depends on the precision parameters used to represent the feature maps and trained parameters. Well-crafted precision parameters are expected to give accuracy similar to accuracy obtained from a single precision model.

What's new in CHaiDNN-v2

4x GOPS compared to CHaiDNN-v1 (2017.4) (Performance numbers)
2x MAC on DSPs at int6
Double-Pumped DSPs allowing the DSPs to be clocked at twice the core clock (Some configs can go upto 350/700Mhz)
Introducing DietChai - A miniature version of CHai for smaller MPSoC/ Zynq devices
128, 256, 512, 1024 DSP design configs verified for ZU9
Support for URAM
128, 256, 512 DSP configs verified for ZU7
ModelZoo of 6 networks at int8 and int6 precision
Support for two quantization modes - Dynamic fixed point and Xilinx Quantizer
Enhanced API to enable better hardware- software partitioning for users
Support for software custom layer plug-ins
Fully Connected layers on CPU
More documentation

Performance Benchmarks(fps)

Network	Xilinx CHai w/ 1024DSP @ 250/500MHz (Measured on ZU9)	Nvidia Jetson TX2 @ 1.3GHz*
GoogleNet-6bit w/o FC	220	Googlenet-16FP: 201
GoogleNet-6bit w/ FC	207
GoogleNet-8bit w/o FC	151
GoogleNet-8bit w/ FC	145
Alexnet-6bit w/o FC	606	Alexnet-16FP: 250
Alexnet-6bit w/ FC	10
Alexnet-8bit w/o FC	390
Alexnet-8bit w/ FC	10

^{* Source: https://devblogs.nvidia.com/jetson-tx2-delivers-twice-intelligence-edge/}

Hardware and Software Requirements

The CHaiDNN library is designed to work with Zynq UltraScale+ MPSoCs. The library has been verified on zcu102 and zcu104 boards. Xilinx SDSoC 2018.2 Development Environment is required to work with the library.

How to Download the Repository

To get a local copy of the CHaiDNN repository, configure git-lfs and then, clone this repository to the local system with the following command:

git clone https://github.com/Xilinx/CHaiDNN.git CHaiDNN

Where CHaiDNN is the name of the directory where the repository will be stored on the local system. This command needs to be executed only once to retrieve the latest version of the CHaiDNN library.

GitHub Repository Structure

CHaiDNN/
|
|-- CONTRIBUTING.md
|-- LICENSE
|-- README.md
|-- SD_Card
|   |-- lib
|   |-- cblas
|   |-- images
|   |-- opencv
|   |-- protobuf
|   |-- zcu102
|   `-- zcu104
|-- design
|   |-- build
|   |-- conv
|   |-- deconv
|   |-- pool
|   `-- wrapper
|-- docs
|   |-- API.md
|   |-- BUILD_USING_SDX_GUI.md
|   |-- CONFIGURABLE_PARAMS.md
|   |-- CUSTOM_PLATFORM_GEN.md
|   |-- HW_SW_PARTITIONING.md
|   |-- MODELZOO.md
|   |-- PERFORMANCE_SNAPSHOT.md
|   |-- QUANTIZATION.md
|   |-- RUN_NEW_NETWORK.md
|   |-- SOFTWARE_LAYER_PLUGIN.md
|   |-- SUPPORTED_LAYERS.md
|   `-- images
|-- software
|   |-- bufmgmt
|   |-- checkers
|   |-- common
|   |-- custom
|   |-- example
|   |-- imageread
|   |-- include
|   |-- init
|   |-- interface
|   |-- scheduler
|   |-- scripts
|   |-- swkernels
|   `-- xtract
`-- tools
    |-- SETUP_TOOLS.md
    `-- tools.zip

Run Inference

Using Pre-built binaries

To run inference on example networks, follow these steps:

Download the example network 6-bit GoogleNet with Xilinx Quantization scheme. More networks are available as part of the ModelZoo.
Place the downloaded and unzipped contents at "SD_Card/models" directory. Create SD_Card/models directory if not present already.
Copy the required contents of "SD_Card" folder into a SD-Card.
- opencv
- protobuf
- cblas
- images
- bit-stream, boot loader, lib & executables (either from SD_Card/zcu102 or SD_Card/zcu104)
Insert the SD-Card and power ON the board.

📌 NOTE: A serial port emulator (Teraterm/Minicom) is required to interface the user commands to the board
Attach a USB-UART cable from the board to the host PC. Set the UART serial port to
```
Baud rate: 115200
Data: 8 bit
Parity: none
Stop: 1 bit
Flow control: none
```

After boot sequence, set LD_LIBRARY_PATH env variable.

export OPENBLAS_NUM_THREADS=2
export LD_LIBRARY_PATH=lib/:opencv/arm64/lib/:protobuf/arm64/lib:cblas/arm64/lib

Create a folder "out" inside the network directory to save the outputs sh cd /mnt mkdir models/<network>/out
Execute "*.elf" file to run inference
- The format for running these example networks is described below:
```
./<example network>.elf <quantization scheme> <bit width> <img1_path> <img2_path>
```
- For GoogleNet 6-bit inference with Xilinx quantization scheme execute the following
```
./googlenet.elf Xilinx 6 images/camel.jpg images/goldfish.JPEG
```
Sync after execution
```
cd /
sync
umount /mnt
```
Output will be written into text file inside respective output folders.
```
Ex : models/<network>/out
```

📌 NOTE: Failing to run sync might corrupt the file system and cause crash on subsequent runs.

📌 NOTE: For running inference on a new network, please follow the instructions in Run new Network using CHaiDNN.

Build from Source

CHaiDNN can be built using Makefiles OR using SDx IDE. The below steps describe how to build CHaiDNN using Makefiles. For steps to build using SDx IDE, see the instructions in Build using SDx IDE.

Build CHaiDNN Hardware

Please follow the steps to build the design for zcu102 (ZU9 device based board)

Please generate a custom platform with 1x and 2x clocks using the steps described here. With Chai-v2, we now have the DSPs operating at twice the frequency of the rest of the core.
Go to CHaiDNN/design/build folder.

Set SDx tool environment

For BASH:

source <SDx Installation Dir>/installs/lin64/SDx/2018.2/settings64.sh

For CSH

source <SDx Installation Dir>/installs/lin64/SDx/2018.2/settings64.csh

To build the design, run Makefile. (By default this will build 1024 DSP design @ 200/400 MHz)
```
make ultraclean
make
```
📌 NOTE:
- To build DietChai, run make DIET_CHAI_Z=1. This builds a design with 128 compute DSPs and 64-bit AXI interface. Run make DIET_CHAI_ZUPLUS=1 to build a design with 128 compute DSPs and 128-bit AXI interface.
- To exclude deconv Kernel, set DECONV_ENABLE=0 in Makefile. Default is DECONV_ENABLE=1.
- To exclude Pool Kernel, set POOL_ENABLE=0 in Makefile. With this setting, Pooling functionality embedded in Convolution accelerator is used. Default is POOL_ENABLE=1.
- When building DietChai, do not change POOL_ENABLE, DECONV_ENABLE values in Makefile.
After the build is completed, copy the libxlnxdnn.so file and other build files (BOOT.BIN, image.ub and _sds directory) inside build/sd_card to SD_Card directory.
```
make copy
```
The hardware setup is now ready.

📌 NOTE:

The 1024 DSP config was timing closed at 250/500Mhz with an iterative synthesis and P&R strategy. In the first iteration, the design was taken through the SDx flow (all the way till the bitstream Gen) at 200/400Mhz. In the second iteration the post-routed design from the first iteration was re-routed at 250/500Mhz. We believe that this is a general strategy that can be applied for other configs also. We would definitely like to hear from you on this if you are able to crank the frequency further up on other configs with this strategy.

Please note that when you try building some of the configs that are mentioned in the performance table, you might see some negative slack reported by the tools but we encourage you to try the bitstreams generated on hardware for functionality. These timing closure issues can be cleaned up with some special synthesis and P&R strategies. (You are welcome to try the timing-closure strategies that have worked for you in the past on other designs.)

Build CHaiDNN Software

Follow the steps to compile the software stack.

Copy libxlnxdnn.so to SD_Card/lib directory. The libxlnxdnn.so file can be found in the design/build/sd_card directory once the HW build is finished. You can skip this step if have already copied the libxlnxdnn.so file to the suggested directory.

Set the SDx tool environment.

CSH

source <SDx Installation Dir>/installs/lin64/SDx/2018.2/settings64.csh

BASH

source <SDx Installation Dir>/installs/lin64/SDx/2018.2/settings64.sh

Go to the software directory. This contains all the files to generate software libraries (.so).
```
cd <path to CHaiDNN>/software
```
Go to scripts directory, open Makefile and update the SDx_BUILD_PATH variable. See example below.
```
SDx_BUILD_PATH = <SDx Installation Dir>/installs/lin64/SDx/2018.2
```
Now run the following commands.
```
make ultraclean
make
```
📌 NOTE:
- To build DietChai, run make DIET_CHAI_Z=1. This builds a design with 128 compute DSPs and 64-bit AXI interface. Run make DIET_CHAI_ZUPLUS=1 to build a design with 128 compute DSPs and 128-bit AXI interface.
- To exclude deconv Kernel, set DECONV_ENABLE=0 in Makefile. Default is DECONV_ENABLE=1.
- To exclude Pool Kernel, set POOL_ENABLE=0 in Makefile. With this setting, Pooling functionality embedded in Convolution accelerator is used. Default is POOL_ENABLE=1.
- When building DietChai, do not change POOL_ENABLE, DECONV_ENABLE values in Makefile.
📌 NOTE: Ensure that the software and the hardware are build with the same settings.
Make will copy all executables to SD_Card directory and all .so files to SD_Card/lib directory.
Now, we are set to run inference. Follow the steps mentioned in "run inference using pre-build binaries"

Additional Resources and Support

For questions and to get help on this project or your own projects, visit the CHaiDNN Github Issues.

License and Contributing to the Repository

The source for this project is licensed under the Apache License 2.0

To contribute to this project, follow the guidelines in the Repository Contribution README

Acknowledgements

Revision History

Date	Readme Version	Release Notes	Tool Version
Feb, 2018	1.0	Initial Xilinx release	SDx-2017.4
June, 2018	2.0	CHaiDNN-v2	SDx-2018.2

Deprecated Features

16-bit activations

chaidnn's People

Contributors

Stargazers

Watchers

Forkers

aaimecn jxhekang ycyep duclongpl jlamperez warmmilk-sudo quartzing jiancunwang eddieburning codeaudit andromem alphabu ml-lab jtcory zhguanw dingbaojin liyang53719 stevebuscemi88 cypox armenth anjaliagarwal8 chongxing shuixo lisliyongming hi-eeprom abidrahmank anithabarri pkurogerjs charudatta10 quentonh c60k28 robocon2011 rezapop hitshark salcanmor lishen565 michalhusejko cuauhtemoc-amdg tsingjinyun efraim ksd777 vickyiii ngatilio booool ahn-github fullmoon12185 huilichen xiaokaijia1988 lbbtc younghogong kumasento huanpass weizuo27 bennihoffmann rollingstone zgsxwsdxg laoyingbu davey8086 tjlt leon-fudan xw2333 nhorcher fengwucb rhapso chang-steve qingzengsong syaffa tuanho27 ghimiredhikura hectorkutleng jwy-jump fivezhao littleswig hpollittsmith maxpark cuongdv1 mpa46 zhaoran90 yindongqing ycwu133 mikasathebest honorpeter davidws1972 elegz leowong686 liwenshen liuqiaoping7 srkm009 tg12306 niklaslauf shenchena vivid30 catonblack ishida66 fnatu srf1986 funnyjimmy scinfipco remember08 fenyesb

chaidnn's Issues

Support for large image sizes

Hi,

I think most of the prototxt of the sample corresponds to the image size of 224 x 224.

name: "VGG_ILSVRC_16_layers"
layer {
  name: "data"
  type: "Input"
  top: "data"
  input_param {
    shape {
      dim: 1
      dim: 3
      dim: 224
      dim: 224
    }
  }
}

I am experimenting with a network with a larger size (eg 480 x 600).

layer {
  name: "data"
  type: "Input"
  top: "data"
  input_param {
    shape {
      dim: 1
      dim: 3
      dim: 480
      dim: 600
    }
  }
}

However, when executed on this network, there is no response from PoolTop.

The definition of Pooling seems to be limited to 480 x 480.

design/pool/include/maxpool_config.h

#define OUTWIDTH	　480
#define OUTHEIGHT　　　　　480

So, I changed the OUTWIDTH and OUTHEIGHT, but it was the same result.

#define OUTWIDTH	　480*2
#define OUTHEIGHT　　　　　480*2

Is it not enough to make the above changes to correspond to a large image size?
Or is there a mistake in correspondence?

Thanks.

Questions about the size of the .elf files and build time.

Hi all, I've test the example elf in our project and they work well. Then I had builded the project in SDx GUI and found that the elf was about 10MB. But the example elf in CHaiDNN project is about 59kB. Why my elf file which produced by SDx is much larger than yours?
The six example elf you provided could work well on the same FPGA bitstream. So I think the example elf has few relationship about the bitstream. I don't want to rebuild the whole project just as I modified the application code, because it would take a very long time to complete the build procedure. Do you have any good way to shorten the rebuild time?
Thanks a lot!

ERROR: slashes ( / ) are removed in some routes

Hi guys,

I have tried to make a build following the CHaiDNN guide and I'm getting this error.

If you take a look to the error ( "C:CHaiDNNCHaiDNN_v2srcconvscriptsmcps.tcl"), you'll notice that all the "/" are removed.

Any idea to fix this error?

===>The following messages were generated while  Compiling (top level synthesis checkpoint) dynamic region Log file: C:/CHaiDNN/CHaiDNN_v2/Debug/_sds/p0/vivado/prj/prj.runs/synth_1/runme.log  :
ERROR: [VPL-1] couldn't read file "C:CHaiDNNCHaiDNN_v2srcconvscriptsmcps.tcl": no such file or directory
ERROR: [VPL 60-704] Integration error, One or more synthesis runs failed during dynamic region dcp generation
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling 'C:/Xilinx/SDx/2018.2/bin/vpl   --iprepo C:/CHaiDNN/CHaiDNN_v2/Debug/_sds/iprepo/repo  --iprepo C:/Xilinx/SDx/2018.2/data/ip/xilinx  --platform C:/Xilinx/SDx/2018.2/platforms/zcu104/zcu104.xpfm  --temp_dir C:/CHaiDNN/CHaiDNN_v2/Debug/_sds/p0  --output_dir C:/CHaiDNN/CHaiDNN_v2/Debug/_sds/p0/vpl  --input_file C:/CHaiDNN/CHaiDNN_v2/Debug/_sds/p0/.xsd/top.bd.tcl  --target hw   --save_temps  --kernels PoolTop:XiDeconvTop:XiConvolutionTop:adapter --webtalk_flag SDSoC  --remote_ip_cache C:/CHaiDNN/ip_cache --xp \"param:compiler.skipTimingCheckAndFrequencyScaling=1\" --xp "vivado_prop:run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp \"vivado_prop:run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1\" --xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp \"vivado_prop:run.synth_1.{STEPS.SYNTH_DESIGN.TCL.PRE}={C:\CHaiDNN\CHaiDNN_v2\src\conv\scripts\mcps.tcl}\" --xp \"vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.TCL.PRE}={C:\CHaiDNN\CHaiDNN_v2\src\conv\scripts\mcps.tcl}\" --xp \"param:compiler.deleteDefaultReportConfigs=false\" '
sds++ log file saved as C:/CHaiDNN/CHaiDNN_v2/Debug/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

make: *** [CHaiDNN_v2.elf] Error 1

13:47:19 Build Finished (took 1h:4m:5s.907ms)

Need to modify quantization_param in quantized.prototxt file. But can not parse the prototxt file using caffe.Net

I am making an experiment. I quantized a model. It gives me quantized.prototxt file. It has an extra parameter named quantization_param . So, when trying to parse the file using caffe.Net(), it throws an error mentioning :
[libprotobuf ERROR google/protobuf/text_format.cc:274] Error parsing text-format caffe.NetParameter: 66:22: Message type "caffe.LayerParameter" has no field named "quantization_param".

quantization_param looks like -
quantization_param {
bw_layer_in: 32
bw_layer_out: 32
bw_params: 8
fl_layer_in: 24
fl_layer_out: 20
fl_params: 8
}

How can I access that quantized.prototxt file and modify fields of quantization_param. Do you have any idea ? Can you provide any Python code / Shell script to do this job. Thanks in Advance

How do I find output feature maps results and save to my disk?

I want to know how to save the results of some layers, such as convolution layer's output feature maps and pooling layer?
thanks.

Does CHaiDNN support Faster R-CNN?

Hi, I define a faster r-cnn model followed by RUN_NEW_NETWORK.md, but it can't run correctly.

[libprotobuf ERROR google/protobuf/text_format.cc:299] Error parsing text-format caffe.NetParameter: 3722:25: Message type "caffe.LayerParameter" has no field named "psroi_pooling_param". [EP002] Couldn't Parse the deploy file : /mnt/models/CustomNet/deploy.prototxt

So I want to know if CHAiDNN supports roi layer?

Error on ZC102 board while executing

libprotobuf FATAL ../../SD_Card/protobuf_arm64/include/google/protobuf/repeated_field.h:1418] CHECK failed: (index) < (current_size_):
terminate called after throwing an instance of 'google::protobuf::FatalException'
what(): CHECK failed: (index) < (current_size_):
Aborted

Used the exact code as in https://github.com/Xilinx/CHaiDNN/blob/master/RUN_NEW_NETWORK.md

Different platform

Hello,
Can I execute these examples using a different platform, i.e. zcu104.
I tried implementing it but it gives an error regarding the clock ID. This line in the Makefile is giving this error. "-sds-hw XiConvolutionTop ../../src/conv/example/xi_convolution_top.cpp -clkid 3 -hls-tcl ./config_core2.tcl -sds-end -dmclkid 3 "
Can you tell me what this line means and also how can I change it with respective to zcu104 platform.

Thanks

mcp_const.xdc, support TE0808-04-09-1EE-S StarterKit

Hi,

I reference the issues #43 and #46 because they can be related.

I am building CHaiDNN v2 for TE0808-04-09-1EE-S Starter kit which contains a ZU9EG module.

I have created a custom SDSoC machine for the board and I am able to run CHaiDNN executables (GoogleNet, Alexnet, Resnet and SSD) @100/200Mhz, 1024DSP with the next performance:

Alexnet

./alexnet.elf Xilinx 6 images/camel.jpg images/goldfish.JPEG

[PERFM] Performance with Batching : 5.852938 Images/second

./alexnet.elf Xilinx 8 images/camel.jpg images/goldfish.JPEG

[PERFM] Performance with Batching : 5.984368 Images/second

GoogleNet_V1_NoLRN

./googlenet.elf Xilinx 6 images/camel.jpg images/goldfish.JPEG

[PERFM] Performance with Batching : 92.024878 Images/second

./googlenet.elf Xilinx 8 images/camel.jpg images/goldfish.JPEG

[PERFM] Performance with Batching : 62.667814 Images/second

ResNet-50-BNfused

./resnet50.elf Xilinx 6 images/camel.jpg images/goldfish.JPEG

[PERFM] Performance with Batching : 29.733502 Images/second

./resnet50.elf Xilinx 8 images/camel.jpg images/goldfish.JPEG

[PERFM] Performance with Batching : 20.563600 Images/second

VGG-SSD300

./ssd.elf Xilinx 6 images/camel.jpg images/goldfish.JPEG

[PERFM] Performance with Batching : 3.027429 Images/second

./ssd.elf Xilinx 8 images/camel.jpg images/goldfish.JPEG

[PERFM] Performance with Batching : 2.286070 Images/second

Now I would like to get a better performance and approximate to the ones listed in the performance tables but when I try to compile for another clock frequencies I am different problems.

To try to solve this problems I have opened the created vivado.log and there are some points that I have not very clear:

1.- When SDSoC sources mcp_const.tcl I have this Critical Warnings

CRITICAL WARNING: [Vivado 12-4739] set_multicycle_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*din6_buf*" && PRIMITIVE_TYPE =~ REGISTER.*.* }]'. [/home/jlamperez/Proyectos/CHaiDNN_250_500/design/conv/scripts/mcp_const.xdc:6]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-508] No pins matched 'zcu102_i/clk_wiz_0/inst/plle4_adv_inst/CLKOUT0'. [/home/jlamperez/Proyectos/CHaiDNN_250_500/design/conv/scripts/mcp_const.xdc:7]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/jlamperez/Proyectos/CHaiDNN_250_500/design/conv/scripts/mcp_const.xdc:7]
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins zcu102_i/clk_wiz_0/inst/plle4_adv_inst/CLKOUT0]'. [/home/jlamperez/Proyectos/CHaiDNN_250_500/design/conv/scripts/mcp_const.xdc:7]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.

So, in mcp_const.xdc I am seeing that it references to zcu102_i, do I need to modify this constraint file? Why is working @100/200 if I haven't modify this file for the starter kit?

2.- Can this damage the board?

CRITICAL WARNING: [Vivado 12-4430] You are lowering the severity from an ERROR. This can potentially lead to board damage or other functionality issues on hardware. If this is not desired, please run 'reset_property SEVERITY [get_drc_checks HDPR-5]' to undo this change.

3.- This is the one explained in issue #46

problem implementing dynamic region, route_design ERROR
    while executing
"error {problem implementing dynamic region, route_design ERROR}"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 error [list $msg]"
    (procedure "error2file" line 12)
    invoked from within
"error2file $cwd "problem implementing dynamic region, $run_status" "
    (procedure "ocl_util::single_project_flow_unip" line 234)
    invoked from within
"ocl_util::single_project_flow_unip $dsa_info $config_info $clk_info $debug_profile_info"
    (file "/home/jlamperez/Proyectos/CHaiDNN_250_500/design/build/_sds/p0/vivado/ipirun.tcl" line 207)

Can someone help me debugging this? I can share custom SDSoC platform if needed.

I would like to write some tutorials about this work once the platform is more stable.

Thanks,

Jorge

the accuracy of VGGSSD on CHaiDNN-v2 is not good

I have question related to mAP,
How did you measure mAP of VGGSSD?
I checked the accuracy of VGGSSD for two images camel.jpg and fish.jpg but it is too bad

I captured some results as below, confident_threshold = 0.25
-> for Camel.jpg
//label-id, name, score, xmin, ymin, xmax, ymax
15 person 0.379514 597 1062 676 1305
9 chair 0.295174 524 894 618 1139
18 sofa 0.292740 835 933 937 1076
1 aeroplane 0.284229 111 255 213 379
3 bird 0.275507 133 243 221 350
15 person 0.270707 639 660 785 876
11 diningtable 0.268451 132 403 333 646
3 bird 0.258317 192 272 265 339
16 pottedplant 0.250684 1080 304 1166 503

-> for Fish.jpg
Detection num = 200
//label-id, name, score, xmin, ymin, xmax, ymax
9 chair 0.353430 353 162 415 212
16 pottedplant 0.326995 339 205 419 232
2 bicycle 0.301073 345 223 416 273
15 person 0.285968 281 229 319 278
15 person 0.285354 309 227 342 264
9 chair 0.278175 327 196 367 226
9 chair 0.267440 248 96 316 160
15 person 0.266520 277 241 341 290
15 person 0.254333 309 223 377 269
15 person 0.253709 252 200 322 254

Please help
Thank you very much!

Integration error, problem implementing dynamic region

Hi,

I am trying to build CHaiDNN with SDx but I have the issue below：

ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, opt_design ERROR
make: *** [test_alexnet.elf] Error 1
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/home/zhoufanyu/Programes/Xilinx/SDx/2017.4/bin/vpl --iprepo /home/zhoufanyu/workspace/test_alexnet/Debug/_sds/iprepo/repo --iprepo /home/zhoufanyu/Programes/Xilinx/SDx/2017.4/data/ip/xilinx --platform /home/zhoufanyu/Programes/Xilinx/SDx/2017.4/platforms/zcu102/zcu102.xpfm --temp_dir /home/zhoufanyu/workspace/test_alexnet/Debug/_sds/p0 --output_dir /home/zhoufanyu/workspace/test_alexnet/Debug/_sds/p0/vpl --input_file /home/zhoufanyu/workspace/test_alexnet/Debug/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels PoolTop:xiSgemvTop:XiDeconvTop:XiConvolutionTop --webtalk_flag SDSoC --remote_ip_cache /home/zhoufanyu/workspace/ip_cache --xp "param:compiler.skipTimingCheckAndFrequencyScaling=1" '
sds++ log file saved as /home/zhoufanyu/workspace/test_alexnet/Debug/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

makefile:60: recipe for target 'test_alexnet.elf' failed

Could anyone help? Thanks.

CHaiDNN on KCU1500

Hi, we want to run CHaiDNN on KCU1500. Then is there any plan to support KCU1500?

Access multiple bootom output results in Software Layer Plugin

Hi, I've read the steps to create a custom software layer plugin, which says "custom layer can take multiple bottom blobs, but only one top blob", The example code accesses a bottom result by In_ptr = (float*)xchange->in_ptrs[0], but how to access multiple bottom results?

By the way, can you introduce the differences between in_ptr[0], in_ptr[1], in_ptr[2], in_ptr[3], and in_ptr[4]

thank for your reply.

Problem while building src in SDx

Hi, I've import the code and build the CHaiDNN as https://github.com/Xilinx/CHaiDNN.
But something wrong when I tried to build the project. The detail of console output is below:

Could you tell me how to solve this problem ?Thanks very much.

Build failed, can anyone help?

Hi,
I am trying to build ChaiDNN with Ubuntu 16.04, but I get sds.log this:

...
[03:10:16] Phase 10 Post Router Timing
[03:10:16] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 36m 01s

[03:10:16] Starting bitstream generation..

ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, write_bitstream ERROR
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/home/ssssspe/FPGA/SDx/2017.4/bin/vpl --iprepo /home/ssssspe/song/FPGA/CHaiDNN/design/scripts/kernel/_sds/iprepo/repo --iprepo /home/ssssspe/FPGA/SDx/2017.4/data/ip/xilinx --platform /home/ssssspe/FPGA/SDx/2017.4/platforms/zcu102/zcu102.xpfm --temp_dir /home/ssssspe/song/FPGA/CHaiDNN/design/scripts/kernel/_sds/p0 --output_dir /home/ssssspe/song/FPGA/CHaiDNN/design/scripts/kernel/_sds/p0/vpl --input_file /home/ssssspe/song/FPGA/CHaiDNN/design/scripts/kernel/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels XiConvolutionTop:PoolTop:xiSgemvTop:XiDeconvTop --webtalk_flag SDSoC --xp "param:compiler.skipTimingCheckAndFrequencyScaling=1" '
sds++ log file saved as /home/ssssspe/song/FPGA/CHaiDNN/design/scripts/kernel/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed
sds++ completed at Tue May 29 04:39:02 CST 2018

the vivado.log:

...
Finished Running Vector-less Activity Propagation
102 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:08:03 ; elapsed = 00:27:16 . Memory (MB): peak = 12192.148 ; gain = 322.953 ; free physical = 171 ; free virtual = 830
INFO: [runtcl-4] Executing : report_route_status -file updated_full_design_route_status.rpt -pb updated_full_design_route_status.pb
report_route_status: Time (s): cpu = 00:00:05 ; elapsed = 00:03:03 . Memory (MB): peak = 12192.148 ; gain = 0.000 ; free physical = 223 ; free virtual = 830
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file updated_full_design_timing_summary_routed.rpt -rpx updated_full_design_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
report_timing_summary: Time (s): cpu = 00:00:53 ; elapsed = 00:02:11 . Memory (MB): peak = 12319.141 ; gain = 126.992 ; free physical = 359 ; free virtual = 732
INFO: [runtcl-4] Executing : report_incremental_reuse -file updated_full_design_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file updated_full_design_clock_utilization_routed.rpt
report_clock_utilization: Time (s): cpu = 00:01:26 ; elapsed = 00:02:13 . Memory (MB): peak = 12319.141 ; gain = 0.000 ; free physical = 217 ; free virtual = 706
Command: write_bitstream -force zcu102_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
/home/ssssspe/FPGA/Vivado/2017.4/bin/loader: line 194: 2570 Killed "$RDI_PROG" "$@"
[Tue May 29 04:32:32 2018] impl_1 finished
wait_on_run: Time (s): cpu = 02:45:07 ; elapsed = 03:02:46 . Memory (MB): peak = 7468.555 ; gain = 0.000 ; free physical = 7240 ; free virtual = 11668
problem implementing dynamic region, write_bitstream ERROR
while executing
"error {problem implementing dynamic region, write_bitstream ERROR}"
("uplevel" body line 1)
invoked from within
"uplevel 1 error [list $msg]"
(procedure "error2file" line 12)
invoked from within
"error2file $cwd "problem implementing dynamic region, $run_status" "
(procedure "ocl_util::create_bitstreams_unip" line 112)
invoked from within
"ocl_util::create_bitstreams_unip $dsa_info $config_info $clk_info"
(file "/home/ssssspe/song/FPGA/CHaiDNN/design/scripts/kernel/_sds/p0/_vpl/ipi/ipirun.tcl" line 188)
INFO: [Common 17-206] Exiting Vivado at Tue May 29 04:33:42 2018...

Can you help me?

'clock_start': symbol multiply defined error building CHaiDNN using SDx IDE

Hi,

I am trying to build CHaiDNN with SDx but I have the next issue

Building target: CHaiDNN_new.elf
Invoking: SDS++ Linker
sds++ -xp param:compiler.skipTimingCheckAndFrequencyScaling=1 -L/home/jlamperez/Proyectos/CHaiDNN/CHaiDNN/SD_Card/opencv_arm64/lib -L/home/jlamperez/Proyectos/CHaiDNN/CHaiDNN/SD_Card/protobuf_arm64/lib --remote_ip_cache /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/ip_cache -o "CHaiDNN_new.elf"  ./src/software/xtract/caffe.pb.o ./src/software/xtract/caffe_network_parser.o ./src/software/xtract/hw_settings.o ./src/software/xtract/xgraph.o ./src/software/xtract/xi_funcs.o ./src/software/xtract/xtract_opt.o  ./src/software/swkernels/xi_crop.o ./src/software/swkernels/xi_nms_top.o ./src/software/swkernels/xi_norm_top.o ./src/software/swkernels/xi_permute_top.o ./src/software/swkernels/xi_swsoftmax_top.o  ./src/software/scheduler/xi_scheduler.o ./src/software/scheduler/xi_thread_routines.o ./src/software/scheduler/xi_utils.o  ./src/software/interface/xi_interface.o  ./src/software/init/xi_init.o  ./src/software/include/xchange_structs.o  ./src/software/imageread/xi_input_image.o  ./src/software/example/advanced_resnet50_ex.o ./src/software/example/alexnet_ex.o ./src/software/example/alexnetfcn_ex.o ./src/software/example/googlenet_ex.o ./src/software/example/ssd_ex.o ./src/software/example/vgg_ex.o  ./src/software/common/xi_kernels.o  ./src/software/checkers/checkers.o  ./src/software/bufmgmt/xi_buf_mgmt.o  ./src/design/utils/common/dnn_wrapper.o  ./src/design/src/pool/example/pooling_layer_dp_2xio_top.o  ./src/design/src/gemv/example/xi_sgemv_top.o  ./src/design/src/deconv/example/xi_deconv_top.o  ./src/design/src/conv/example/xi_convolution_top.o   -lopencv_core -llzma -ltiff -lpng16 -lz -ljpeg -lopencv_imgproc -lopencv_imgcodecs -ldl -lrt -lwebp -lprotobuf -dmclkid 3  -sds-sys-config a53_linux -sds-proc a53_linux -sds-pf "zcu102"
Removing implementation files from previous run
Analyzing object files
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/xtract/caffe.pb.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/xtract/caffe_network_parser.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/xtract/hw_settings.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/xtract/xgraph.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/xtract/xi_funcs.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/xtract/xtract_opt.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/swkernels/xi_crop.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/swkernels/xi_nms_top.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/swkernels/xi_norm_top.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/swkernels/xi_permute_top.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/swkernels/xi_swsoftmax_top.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/scheduler/xi_scheduler.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/scheduler/xi_thread_routines.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/scheduler/xi_utils.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/interface/xi_interface.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/init/xi_init.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/include/xchange_structs.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/imageread/xi_input_image.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/example/advanced_resnet50_ex.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/example/alexnet_ex.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/example/alexnetfcn_ex.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/example/googlenet_ex.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/example/ssd_ex.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/example/vgg_ex.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/common/xi_kernels.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/checkers/checkers.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/software/bufmgmt/xi_buf_mgmt.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/design/utils/common/dnn_wrapper.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/design/src/pool/example/pooling_layer_dp_2xio_top.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/design/src/gemv/example/xi_sgemv_top.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/design/src/deconv/example/xi_deconv_top.o
... /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/src/design/src/conv/example/xi_convolution_top.o
Generating data motion network
ERROR: Linking globals named 'clock_start': symbol multiply defined!
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/home/jlamperez/Vivado/Vivado2017.4/SDx/SDx/2017.4/bin/llvm-link -o /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/sds_all.o /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/xtract/caffe.pb.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/xtract/caffe_network_parser.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/xtract/hw_settings.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/xtract/xgraph.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/xtract/xi_funcs.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/xtract/xtract_opt.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/swkernels/xi_crop.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/swkernels/xi_nms_top.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/swkernels/xi_norm_top.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/swkernels/xi_permute_top.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/swkernels/xi_swsoftmax_top.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/scheduler/xi_scheduler.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/scheduler/xi_thread_routines.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/scheduler/xi_utils.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/interface/xi_interface.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/init/xi_init.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/include/xchange_structs.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/imageread/xi_input_image.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/example/advanced_resnet50_ex.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/example/alexnet_ex.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/example/alexnetfcn_ex.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/example/googlenet_ex.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/example/ssd_ex.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/example/vgg_ex.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/common/xi_kernels.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/checkers/checkers.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/software/bufmgmt/xi_buf_mgmt.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/design/utils/common/dnn_wrapper.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/design/src/pool/example/pooling_layer_dp_2xio_top.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/design/src/gemv/example/xi_sgemv_top.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/design/src/deconv/example/xi_deconv_top.s /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/.llvm/./src/design/src/conv/example/xi_convolution_top.s'
sds++ log file saved as /home/jlamperez/Proyectos/CHaiDNN/SDx_ws/CHaiDNN_new/Debug/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

makefile:60: fallo en las instrucciones para el objetivo 'CHaiDNN_new.elf'
make: *** [CHaiDNN_new.elf] Error 1

It seems that clock_start symbol is multiply defined. Do I need to add something else to the linker appart from what is written in the build CHaiDNN with SDx?

Thanks,

Jorge

report

Hi,
In new network tutorial, can I also generate the report for the network? and how?

Thank you

output of MobilenetSSD-300 on CHaiDNN is wrong

Hi guys
I am trying to convert MobilenetSSD-300 caffe model to CHaiDNN
I followed guidelines at https://github.com/Xilinx/CHaiDNN/blob/master/docs/RUN_NEW_NETWORK.md
But the detection output seems wrong as below. Do you have any idea for this issue?

test image: Camel.jpg
2 bicycle 1.000000 -407 1352 672 1648
2 bicycle 1.000000 1082 1336 1445 1812
2 bicycle 1.000000 720 1363 1624 1689
11 diningtable 1.000000 1126 1177 1395 1862
2 bicycle 0.500000 -64 189 627 331
2 bicycle 0.500000 876 1239 1690 1919
8 cat 0.500000 -64 189 627 331
16 pottedplant 0.500000 876 1239 1690 1919
2 bicycle 0.333333 -64 1318 304 1802
2 bicycle 0.333333 -208 1168 593 1871
10 cow 0.333333 -64 1318 304 1802
13 horse 0.333333 -64 1318 304 1802
13 horse 0.333333 -208 1168 593 1871
16 pottedplant 0.333333 -208 1168 593 1871

test image: Fish.jpg
Detection num = 14
2 bicycle 1.000000 -150 273 248 332
2 bicycle 1.000000 401 268 533 365
2 bicycle 1.000000 266 275 601 341
11 diningtable 1.000000 416 237 516 375
2 bicycle 0.500000 -23 39 232 67
2 bicycle 0.500000 320 250 626 387
8 cat 0.500000 -23 39 232 67
16 pottedplant 0.500000 320 250 626 387
2 bicycle 0.333333 -24 266 113 363
2 bicycle 0.333333 -75 235 221 377
10 cow 0.333333 -24 266 113 363
13 horse 0.333333 -24 266 113 363
13 horse 0.333333 -75 235 221 377
16 pottedplant 0.333333 -75 235 221 377

Please help
Thanks in advance!

Iterative synthesis and P&R strategy

Can somebody point me out with some resources of how can I do this iterative strategy?

Do I need to open Vivado design and make it? How is created libxlnxdnn.so if I build from Vivado and with the hardware Makefile?

Thanks!

Error in running Estimate Performance in SDSoc

Thanks for providing the program, I have successfully run on the ZCU102 development board.Now I want to run the Estimate Performance in SDSoc, but there is always an error as shown in the following figure. How can I solve it? Thank you!

INFO: [DMAnalysis 83-4494] Analyzing hardware accelerators...
ERROR: [DMAnalysis 83-4430] Performance estimation not supported for "PoolTop". Possible workaround: Consider modifying the loop boundary in the function to be compile-time constant, or use Vivado HLS's tripcount pragma.
Data motion generation exited with return code -3
performance estimation not supported
sds++ log file saved as /home/daichong/Work/SDx_project/CHaiDNN1/Release/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

¿start/end layer in the graph1 & graph2?

Hi guys,

I'm trying to run a new network. I've analyzed all the examples from /software/example/ and followed the "Running a Network using CHaiDNN" and there's a part which is missing in that guide.

In all the network examples from /software/example/ we can find this piece of code:

	//# start/end layer in the graph1
	string start_layer_graph1 = "";
	string end_layer_graph1   = "pool5/7x7_s1";

	//# start/end layer in the graph2
	string start_layer_graph2 = "loss3/classifier";
	string end_layer_graph2   = "";

Where the layers in end_layer_graph1 and start_layer_graph2 change in every network.
I'm trying to inference a new network and I don't know what to write in end_layer_graph1 and start_layer_graph2.

How do you know which layers do you have to place in those 2 variables?

Thanks in advance!

Problem about Ristretto?

Hi, I've tried to run the squeezenet in accordance with "Ristretto Quantization User Guide", and get my quantized.prototxt. When I ran my squeezenet.elf on board something was wrong at parsing pool10 whose global_pooling is true and type is AVE. The detail result is below:

And I checked my quantized.prototxt and found that there is no quantization_param in layer pool10. Can you help me to solve this problem ?

Ristretto for ssd?

How do you use ristretto to determine the precision parameters for ssd? Can ristretto fine-tune detection models like ssd? Thinks...

New project

Hi,
I have a project involving image processing and neural networks which I want to port to Xilinx platform zcu104_rv_ss. It was made using LeNet and I have successfully got the executable file for the same. Now I have a main code for which I want to get the elf file. Can you help me with that as I am unable to find any documentation regarding that.

Thanks,
Anjali

Problems caused by adding "opencv_videoio"

Hello there
I would like to add the "VideoCapture" function using the opencv library provided here.
I added "videoio.hpp" as follows.

#if 1//def SDSCC
#undef ARM_NEON
#undef __ARM_NEON
#include <opencv2/core/core.hpp>
#include <opencv2/imgproc/imgproc.hpp>
#include <opencv2/highgui/highgui.hpp>
#include <opencv2/videoio/videoio.hpp>
#define ARM_NEON
#define __ARM_NEON
#else
#include <opencv2/core.hpp>
#include <opencv2/imgproc.hpp>
#include <opencv2/highgui.hpp>
#include <opencv2/videoio.hpp>
#endif

Added "opencv_videoio" in SDS++Linker->Libraries->Libraries(-l)
But when I compile it cannot be compiled successfully.

10:09:27 **** Incremental Build of configuration Debug for project CHaiDNN_ly_opencv_o ****
make pre-build main-build
sdsoc_make_clean Debug

Building target: CHaiDNN_ly_opencv_o.elf
Invoking: SDS++ Linker
sds++ -xp param:compiler.skipTimingCheckAndFrequencyScaling=1 -L/home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib -L/home/liyang/Github/xilinx/CHaiDNN/SD_Card/protobuf_arm64/lib --remote_ip_cache /home/liyang/workspace/CHaiDNN/ip_cache -o "CHaiDNN_ly_opencv_o.elf" ./src/software/xtract/caffe.pb.o ./src/software/xtract/caffe_network_parser.o ./src/software/xtract/hw_settings.o ./src/software/xtract/xgraph.o ./src/software/xtract/xi_funcs.o ./src/software/xtract/xtract_opt.o ./src/software/swkernels/xi_crop.o ./src/software/swkernels/xi_nms_top.o ./src/software/swkernels/xi_norm_top.o ./src/software/swkernels/xi_permute_top.o ./src/software/swkernels/xi_swsoftmax_top.o ./src/software/scheduler/xi_scheduler.o ./src/software/scheduler/xi_thread_routines.o ./src/software/scheduler/xi_utils.o ./src/software/interface/xi_interface.o ./src/software/init/xi_init.o ./src/software/include/xchange_structs.o ./src/software/imageread/xi_input_image.o ./src/software/example/ssd_ex.o ./src/software/common/xi_kernels.o ./src/software/checkers/checkers.o ./src/software/bufmgmt/xi_buf_mgmt.o ./src/design/utils/common/dnn_wrapper.o ./src/design/src/pool/example/pooling_layer_dp_2xio_top.o ./src/design/src/gemv/example/xi_sgemv_top.o ./src/design/src/deconv/example/xi_deconv_top.o ./src/design/src/conv/example/xi_convolution_top.o -lopencv_core -llzma -ltiff -lpng16 -lz -ljpeg -lopencv_imgproc -lopencv_imgcodecs -ldl -lrt -lwebp -lprotobuf -lopencv_videoio -dmclkid 1 -sds-sys-config a53_linux -sds-proc a53_linux -sds-pf "zcu102"
Validating feature ap_sdsoc
License available for feature ap_sdsoc
Your ap_sdsoc license expires in 4 day(s)
Removing implementation files from previous run
Analyzing object files
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/caffe.pb.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/caffe_network_parser.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/hw_settings.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/xgraph.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/xi_funcs.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/xtract_opt.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_crop.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_nms_top.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_norm_top.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_permute_top.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_swsoftmax_top.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/scheduler/xi_scheduler.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/scheduler/xi_thread_routines.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/scheduler/xi_utils.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/interface/xi_interface.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/init/xi_init.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/include/xchange_structs.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/imageread/xi_input_image.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/example/ssd_ex.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/common/xi_kernels.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/checkers/checkers.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/bufmgmt/xi_buf_mgmt.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/utils/common/dnn_wrapper.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/src/pool/example/pooling_layer_dp_2xio_top.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/src/gemv/example/xi_sgemv_top.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/src/deconv/example/xi_deconv_top.o
... /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/src/conv/example/xi_convolution_top.o
Using prebuilt hardware
Skipping block diagram (BD), address map, port information and device registration for partition 0
Prepare hardware access API functions
Create accelerator stub functions
Compile hardware access API functions
Compile accelerator stub functions
Enable generation of boot files
Compile hardware access API functions
Link application ELF file
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libgobject-2.0.so.0, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found ( Try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libglib-2.0.so.0, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found ( Try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libgstreamer-1.0.so.0, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found ( Try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libgstapp-1.0.so.0, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found ( Try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libgstriff-1.0.so.0, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found ( Try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libgstpbutils-1.0.so.0, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found ( Try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libv4l1.so.0, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found (try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libv4l2.so.0, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found (try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libavcodec.so.57, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found (try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libavformat.so.57, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found (try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libavutil.so.55, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found (try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libswscale.so.4, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found (try using -rpath or -rpath-link)
/home/liyang/soft/xilinx/SDK/2017.4/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/6.2.1/../../.. /../aarch64-linux-gnu/bin/ld: warning: libgphoto2.so.6, needed by /home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib/libopencv_videoio.so, not found (try using -rpath or -rpath-link)
...
...
...
collect2: error: ld returned 1 exit status
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling 'aarch64-linux-gnu-g++ /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/caffe.pb.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/caffe_network_parser.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/hw_settings.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/xgraph.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/xi_funcs.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/xtract/xtract_opt.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_crop.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_nms_top.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_norm_top.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_permute_top.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/swkernels/xi_swsoftmax_top.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/scheduler/xi_scheduler.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/scheduler/xi_thread_routines.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/scheduler/xi_utils.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/interface/xi_interface.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/init/xi_init.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/include/xchange_structs.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/imageread/xi_input_image.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/example/ssd_ex.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/common/xi_kernels.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/checkers/checkers.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/software/bufmgmt/xi_buf_mgmt.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/utils/common/dnn_wrapper.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/src/pool/example/pooling_layer_dp_2xio_top.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/src/gemv/example/xi_sgemv_top.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/src/deconv/example/xi_deconv_top.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/src/design/src/conv/example/xi_convolution_top.o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/_sds/swstubs/portinfo.o -L/home/liyang/Github/xilinx/CHaiDNN/SD_Card/opencv_arm64/lib -L/home/liyang/Github/xilinx/CHaiDNN/SD_Card/protobuf_arm64/lib -lopencv_core -llzma -ltiff -lpng16 -lz -ljpeg -lopencv_imgproc -lopencv_imgcodecs -ldl -lrt -lwebp -lprotobuf -lopencv_videoio -L /home/liyang/soft/xilinx/SDx/2017.4/target/aarch64-linux/lib -L/home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/_sds/swstubs -Wl,--start-group -Wl,--end-group -Wl,--start-group -lpthread -lsds_lib -lxlnk_stub -Wl,--end-group -o /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/_sds/swstubs/CHaiDNN_ly_opencv_o.elf'
sds++ log file saved as /home/liyang/workspace/CHaiDNN/CHaiDNN_ly_opencv_o/Debug/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

makefile:60: recipe for target 'CHaiDNN_ly_opencv_o.elf' failed

I try to add those libraries in the warning. However, "libgobject-2.0.so.0" was not found in the provided directory
How can I solve this problem?
Is there a problem with the opencv library or is there a problem with my setup?
What compiler is used by this opencv library. If I want to compile the opencv library myself, which compiler should I use?
Aarch64-linux-gnu-g++? (mentioned in the SDSoC error)
Arm-linux-gnueabihf-g++ ? (found in petalinux)

Can't compile latest version.

Hi,

I checked out latest version. (8 KERNEL PROC Changes)

But I couldn't compile it using SDx IDE.
My Platform is zcu102.

An error related to arm_neon occurs.

/opt/Xilinx/SDK/2018.2/gnu/aarch64/lin/aarch64-linux/lib/gcc/aarch64-linux-gnu/7.2.1/include/arm_neon.h:31:13: warning: unknown pragma ignored [-Wunknown-pragmas]
#pragma GCC target ("+nothing+simd")
            ^
/opt/Xilinx/SDK/2018.2/gnu/aarch64/lin/aarch64-linux/lib/gcc/aarch64-linux-gnu/7.2.1/include/arm_neon.h:38:9: error: unknown type name '__Int8x8_t'
typedef __Int8x8_t int8x8_t;
        ^
/opt/Xilinx/SDK/2018.2/gnu/aarch64/lin/aarch64-linux/lib/gcc/aarch64-linux-gnu/7.2.1/include/arm_neon.h:39:9: error: unknown type name '__Int16x4_t'
typedef __Int16x4_t int16x4_t;
        ^
/opt/Xilinx/SDK/2018.2/gnu/aarch64/lin/aarch64-linux/lib/gcc/aarch64-linux-gnu/7.2.1/include/arm_neon.h:40:9: error: unknown type name '__Int32x2_t'; did you mean '__int32_t'?
typedef __Int32x2_t int32x2_t;
 :
 :

I thought that it was necessary to specify "-mfpu = neon" in the compiler option,
I don't know how to specify with the SDSOC ++ compiler.

Or do I have to take another countermeasure?
Please tell me how to resolve.

Custom machine, Integration error, problem implementing dynamic region, route_design ERROR

Hi,

I have seen in issue #12, that this problem is fixed for the new CHaiDNN v2 release but when I tried to use a custom machine I am having it again.

My custom machine has a clock wizard with this frequencies:

When I compile the Makefile with 100Mhz clock everything compiles fine and I am able to run different networks on the board but Integration error occurs when I try to compile for 200Mhz.

Can you tell me @VishalX how did you fix it?

Also with this clocks when I try to compile for 250Mhz I get the next error:

ERROR: [CF2XD 83-23150] No derived clock for platform 'SK0808_zusys_SDSoC' clock domain 'SK0808_zusys_SDSoC_clk_wiz_0_0_clk_out1' for clock id 3 with clock period multiplier = 1 and clock period divisor = 2
WARNING: [CF2XD 83-1006] Invalid clock id -1 for platform SK0808_zusys_SDSoC
ERROR: [CF2XD 83-1392] Illegal port name 'INVALID_ID' for comp 'SK0808_zusys_SDSoC'
ERROR: [CF2XD 83-1307] getPort(INVALID_ID, SK0808_zusys_SDSoC) is null

Any idea of why is this clock invalid if I have it in the clock wizard?

Thanks,

Jorge

What is the accuracy of each neural net?

I checked the deploy.prototxt of the neuralnet provided in the demo file, and found that the LRN layer was removed. This would lead to a greater accuracy decline than the actual Ristretto claims of 1% accuracy.
However, CHaidnn's documentation does not specify how accurate the accuracy is.
Actually, when I run chaidnn on the zynQ board, I see that it shows almost similar results, but how accurate is it?
I would like to know how much of a drop in accuracy compared to the actual caffe model
plus, Are you planning to add an LRN layer in the future?

The CHaiDNN-v2 has worse performance?

I have built the hardware and sofrware code with Xilinx SDx 2018.2 tools successfully. But when I run the GoogleNet with 6-bit weights on ZCU102, the fps can only achieve 33.5, instead of the 220 fps presented in the documents.
The pre-built library works well, achieving a fps of 210 on ZCU102.
I found in the synthesis report that the project only uses about 444 DSPs ???
I am sure that I did not modify any codes in the repo. Could you please address this problem? Or is there anyone that has met the same problem?

DepthwiseConvolutionLayer?

Do you have any plan or suggestion to support DepthwiseConvolutionLayer?

makefile issue

Hi I am trying to build the LeNet for reVISION platform. I wrote the cpp code and the Makefile as was given in the documentation. When I tried running the makefile I am getting this error:

/usr/lib/gcc-cross/aarch64-linux-gnu/5/../../../../aarch64-linux-gnu/bin/ld: cannot find ../../lib/libc.so.6
/usr/lib/gcc-cross/aarch64-linux-gnu/5/../../../../aarch64-linux-gnu/bin/ld: cannot find ../../lib/ld-linux-aarch64.so.1
collect2: error: ld returned 1 exit status
Makefile:17: recipe for target 'LeNet.elf' failed
make: *** [LeNet.elf] Error 1

Although the necessary files are located in the given directory it was not able to locate it.
It would be really nice if you can help me resolve this issue.

Thanks,
Anjali

reVISION platform

I am building the project on Linux 16.04 using the zcu102 platform.

I want to know if it is possible to compile the project with a different platform to include HDMI/Camera input?

I want to use this with the reVISION platform.

When will be the support for zc702 available?

Can I use 2018.1 version of Vivado and Vivado_HLS?

Hi,

My company has 2018.1 version of Vivado only.
I can't install 2018.2 version of Vivado in server because of permission.
Can I use 2018.1 version of Vivado for CHaiDNN?

Thank you.

Best Regards,
HyungDal.

'main': symbol multiply defined error building CHaiDNN using SDx IDE

Following the BUILD_USING_SDX_GUI instructions and working around issue #3 by making clock_start and related variables static, I am getting a final link error with main() being multiply defined:

ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/Xilinx/SDx/2017.4/bin/llvm-link -o /workspace/CHaiDNN/Debug/_sds/.llvm/sds_all.o /workspace/CHaiDNN/Debug/_sds/.llvm/./src/software/xtract/caffe.pb.s ...

The probability that a picture be classified into different categories is equal, but it is normal on PC.

Hi,Thank you for your source, I have successfully run on the board. Now I have a problem. I use VGG16 to fine-tune to classify four kinds of objects. The classification effect on PC is very good, but the result of running on board is that the probabilities of these four classification are the same, that is 0.25. I just changed the modelfile and meanfile to my own, changed the num_output and input picture, the other has not changed.My deploy.prototxt and out.txt files are below.Can you help me? Thank you!
deploy.prototxt.txt
out.txt

ERROR: Linking globals named 'clock_start': symbol multiply defined!

Hi guys,

I've seen #3 and #9 but those solutions did not solve the problem.

I have excluded from the build all the examples files from src/software/example except one and the error ERROR: Linking globals named 'clock_start': symbol multiply defined! is still there as you can see.

Any idea to fix this error?

aarch64-linux-gnu-objcopy -O binary --set-section-flags .xdif=alloc --only-section=.xdif C:/CHaiDNN/CHaiDNN_v2/Release/src/design/conv/src/xi_convolution_top.o C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.cdb/XiConvolutionTop_if.xml
C:/Xilinx/SDx/2018.2/bin/build_xd_ip_db -ip_search 0  -sds-pf C:/CHaiDNN/CHaiDNN_v2/Release/.Xil/zcu104.hpfm  -ip C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_PoolTop_1_0 -ip C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_XiConvolutionTop_1_0 -ip C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_XiDeconvTop_1_0  -o C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.cdb/xd_ip_db.xml  
INFO: Using user-defined path for XILINX_XD environment variable C:/Xilinx/SDx/2018.2
processing accelerators: C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_PoolTop_1_0
ip_dir: C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_PoolTop_1_0
C:/Xilinx/SDx/2018.2/bin/xsltproc --stringparam xpath "spirit:component/spirit:name/text()" C:/Xilinx/SDx/2018.2/scripts/xdcc/xpathValueOf.xsl C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_PoolTop_1_0/component.xml
ip_name: PoolTop
processing accelerators: C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_XiConvolutionTop_1_0
ip_dir: C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_XiConvolutionTop_1_0
C:/Xilinx/SDx/2018.2/bin/xsltproc --stringparam xpath "spirit:component/spirit:name/text()" C:/Xilinx/SDx/2018.2/scripts/xdcc/xpathValueOf.xsl C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_XiConvolutionTop_1_0/component.xml
ip_name: XiConvolutionTop
processing accelerators: C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_XiDeconvTop_1_0
ip_dir: C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_XiDeconvTop_1_0
C:/Xilinx/SDx/2018.2/bin/xsltproc --stringparam xpath "spirit:component/spirit:name/text()" C:/Xilinx/SDx/2018.2/scripts/xdcc/xpathValueOf.xsl C:/CHaiDNN/CHaiDNN_v2/Release/_sds/iprepo/repo/xilinx_com_hls_XiDeconvTop_1_0/component.xml
ip_name: XiDeconvTop
Generating data motion network
C:/Xilinx/SDx/2018.2/bin/llvm-link -o C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/sds_all.o C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/caffe.pb.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/caffe_network_parser.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xgraph.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xi_funcs.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xtract_opt.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xtract_utility.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_crop.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_fc_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_format_converter_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_nms_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_norm_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_permute_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_swsoftmax_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_perf_eval.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_scheduler.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_thread_routines.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_utils.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/interface/xi_interface.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/interface/xi_readwrite_util.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/init/xi_init.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/include/xchange_structs.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/imageread/xi_input_image.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/example/googlenet_ex.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/custom/custom_class.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/common/kernelinfo_class.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/common/xi_kernels.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/checkers/checkers.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/bufmgmt/xi_buf_mgmt.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/wrapper/dnn_wrapper.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/pool/src/pooling_layer_dp_2xio_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/deconv/src/xi_deconv_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/conv/src/xi_convolution_top.s

C:\CHaiDNN\CHaiDNN_v2\Release>C:\Xilinx\SDx\2018.2\llvm-clang\win64\llvm\bin\llvm-link.exe -o C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/sds_all.o C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/caffe.pb.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/caffe_network_parser.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xgraph.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xi_funcs.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xtract_opt.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xtract_utility.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_crop.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_fc_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_format_converter_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_nms_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_norm_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_permute_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_swsoftmax_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_perf_eval.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_scheduler.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_thread_routines.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_utils.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/interface/xi_interface.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/interface/xi_readwrite_util.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/init/xi_init.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/include/xchange_structs.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/imageread/xi_input_image.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/example/googlenet_ex.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/custom/custom_class.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/common/kernelinfo_class.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/common/xi_kernels.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/checkers/checkers.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/bufmgmt/xi_buf_mgmt.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/wrapper/dnn_wrapper.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/pool/src/pooling_layer_dp_2xio_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/deconv/src/xi_deconv_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/conv/src/xi_convolution_top.s 
ERROR: Linking globals named 'clock_start': symbol multiply defined!

C:\CHaiDNN\CHaiDNN_v2\Release>exit /b 1 
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling 'C:/Xilinx/SDx/2018.2/bin/llvm-link -o C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/sds_all.o C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/caffe.pb.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/caffe_network_parser.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xgraph.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xi_funcs.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xtract_opt.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/xtract/xtract_utility.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_crop.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_fc_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_format_converter_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_nms_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_norm_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_permute_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/swkernels/xi_swsoftmax_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_perf_eval.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_scheduler.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_thread_routines.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/scheduler/xi_utils.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/interface/xi_interface.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/interface/xi_readwrite_util.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/init/xi_init.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/include/xchange_structs.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/imageread/xi_input_image.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/example/googlenet_ex.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/custom/custom_class.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/common/kernelinfo_class.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/common/xi_kernels.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/checkers/checkers.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/software/bufmgmt/xi_buf_mgmt.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/wrapper/dnn_wrapper.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/pool/src/pooling_layer_dp_2xio_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/deconv/src/xi_deconv_top.s C:/CHaiDNN/CHaiDNN_v2/Release/_sds/.llvm/./src/design/conv/src/xi_convolution_top.s'
sds++ log file saved as C:/CHaiDNN/CHaiDNN_v2/Release/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed
sds++ completed at Fri Jul 27 12:08:10 +0200 2018

Bitstream Integration error building CHaiDNN Hardware from source

Hi,

I am trying to build CHaiDNN HW from source and when it starts generating the bitstream I have this error

[12:43:53] Starting bitstream generation..

ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, write_bitstream ERROR
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/home/jlamperez/Vivado/Vivado2017.4/SDx/SDx/2017.4/bin/vpl  --iprepo /home/jlamperez/Proyectos/CHaiDNN/CHaiDNN/design/scripts/kernel/_sds/iprepo/repo  --iprepo /home/jlamperez/Vivado/Vivado2017.4/SDx/SDx/2017.4/data/ip/xilinx  --platform /home/jlamperez/Vivado/Vivado2017.4/SDx/SDx/2017.4/platforms/zcu102/zcu102.xpfm  --temp_dir /home/jlamperez/Proyectos/CHaiDNN/CHaiDNN/design/scripts/kernel/_sds/p0  --output_dir /home/jlamperez/Proyectos/CHaiDNN/CHaiDNN/design/scripts/kernel/_sds/p0/vpl  --input_file /home/jlamperez/Proyectos/CHaiDNN/CHaiDNN/design/scripts/kernel/_sds/p0/.xsd/top.bd.tcl  --target hw   --save_temps  --kernels XiConvolutionTop:PoolTop:xiSgemvTop:XiDeconvTop --webtalk_flag SDSoC  --xp "param:compiler.skipTimingCheckAndFrequencyScaling=1" '
sds++ log file saved as /home/jlamperez/Proyectos/CHaiDNN/CHaiDNN/design/scripts/kernel/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

Makefile:77: fallo en las instrucciones para el objetivo 'libxlnxdnn.so'
make: *** [libxlnxdnn.so] Error 1

Any way to solve it?

Thanks in advance,

Jorge

custom layer execution

I already know that CHaiDNN's custom layer only supports two bottom blobs and one top blob, so I save the remaining bottom blob to global memory for custom layer calls.

For Example: the custom layer requires the calculation results of conv1, conv2, conv3, conv4. In prototxt, I pass conv1 and conv2 to the custom layer, and the results of conv3 and conv4 are saved in the global memory or file. When the custom layer is executed, the layer accesses conv1 and conv2 from memory and conv3 and conv4 from global memory or files.

Since CHaiDNN uses hardware and software partitioning and multi-thread parallel execution, how can I be sure that the calculation results of conv3 and conv4 have been saved to global memory during the custom layer execution?

I tried to run it, but it seems that the hardware acceleration part has not yet calculated conv3 and conv4 when executing the custom layer. So I got a wrong calculation result

New network

Hi,
Regarding running a new network tutorial. Can I add my own code to the MyNet.cpp file like some opencv functions to add functionality to my network.

Thanks,
Anjali

Build failed, can anyone help?

Hi,
I am trying to build ChaiDNN with Ubuntu 16.04, but I get sds.log this:

...
[03:10:16] Phase 10 Post Router Timing
[03:10:16] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 36m 01s

[03:10:16] Starting bitstream generation..

the vivado.log:

Different platform: ps_e_S_AXI_HP0_FPD for in1 cannot be found in the platform!

Hi,
I am trying to import CHaiDNN to a xfopencv demo with HDMI input named filter2d, and build CHaiDNN to a shared library. But the platform of filter2d is zcu102_es2_rv_ss, not zcu102.
When I build CHaiDNN without hardware accelerator, there is nothing wrong. When I accelerate the XiConvolutionTop, I get some errors:

WARNING: [DMAnalysis 83-4492] Unable to determine the memory attributes passed to scalar_conv_args of function XiConvolutionTop at /home/ssssspe/FPGA/workspace/filter2d/src/design/utils/common/dnn_wrapper.cpp:59, please use mem_attribute pragma to specify
CRITICAL WARNING: [DMAnalysis 83-4483] Cannot find corresponding HW caller for sds_wait(1); @ /home/ssssspe/FPGA/workspace/filter2d/src/software/scheduler/xi_scheduler.cpp:587, application may die at run time
INFO: [DMAnalysis 83-4444] Scheduling data transfer graph for partition 0
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP0_FPD for in1 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP1_FPD for in2 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP2_FPD for out1 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP3_FPD for out2 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP0_FPD for weights1 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP1_FPD for weights2 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP2_FPD for output1 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP3_FPD for output2 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP2_FPD for input_other1 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP3_FPD for input_other2 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP2_FPD for input_1st cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP2_FPD for bias cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP3_FPD for inp_norm_2 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP3_FPD for inp_norm_3 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP0_FPD for istg_out1 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP1_FPD for istg_out2 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP0_FPD for weights1 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP1_FPD for weights2 cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP0_FPD for input cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP0_FPD for bias cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP0_FPD for output cannot be found in the platform!
ERROR: [DMAnalysis 83-4416] Specified sys_port: ps_e_S_AXI_HP0_FPD for weights1 cannot be found in the platform!
ERROR: [DMAnalysis 83-4445] Failed scheduling data transfer graph!
/home/ssssspe/FPGA/SDx/2017.4/bin/XidanePass: 1: /home/ssssspe/FPGA/SDx/2017.4/bin/XidanePass: gawk: not found
Data motion generation exited with return code 1

errors detected
sds++ log file saved as /home/ssssspe/FPGA/workspace/filter2d/Debug/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

makefile:60: recipe for target 'libfilter2d.so' failed
make: *** [libfilter2d.so] Error 1

Do you have any suggestions? Thanks!

New network inference doesn't work

Hello,

When I try to run my own network, a simple LeNet trained on MNIST, all outputs are barely equal to 0.1 (10 ouputs).

I used the loadImagetoBuffptr function in the main function, with a mean.txt file (0 for each channel because I didn't substract the mean for my training). My input is a 28x28 .png image from the MNIST database, in the RGB (opened as BGR with opencv) format (so the 3 channels are the same).

The network runs well when using python and caffe-ristretto, and all provided .elf examples work.

run a new caffe module ,illegal memory access

when i try a new caffe module .i am done with SDSoC .i put the file in the SD card and run.
there is an ERROR,which is write down below.

ERROR: application performed illegal memory access and is being terminated

and there is a warning :

[libprotobuf INFO google/protobuf/io/coded_stream.cc:610] Reading dangerously large protocol message. If the message turns out to be larger than 2147483647 bytes, parsing will be halted for security reasons. To increase the limit (or to disable these warnings), see CodedInputStream::SetTotalBytesLimit() in google/protobuf/io/coded_stream.h.
[libprotobuf WARNING google/protobuf/io/coded_stream.cc:81] The total number of bytes read was 209274056

i do not how to fix it.please help me.

Can you provide your train_val.prototxt file

Hello,thanks for the source code you provided. Now I have encountered some problems. I hope to refer to the train_val.prototxt file of your googlenet project.I want to know the difference of your train_val.prototxt and the deploy.prototxt file.Can you provide it? Thank you!

MobileNet-SSD run on CHaiDNN v2 fail.

Hi,
I quantize model deloy of Mobilenet-SSD on https://github.com/chuanqi305/MobileNet-SSD
follow Xilinx quantization on this guide: https://github.com/Xilinx/CHaiDNN/blob/master/docs/QUANTIZATION.md
But run failure.
MobileNet-SSD input image pixel is on range [-1:1],
so I set run file quantize is:

./chaidnn_tools_ENV/bin/python2 XportDNN.pyc --quant_type "Xilinx" \
--deploy_model /home/anhnt/CHaiDNN/tools/tools/MobileNet-SSD/deploy.prototxt \
--weights /home/anhnt/CHaiDNN/tools/tools/MobileNet-SSD/MobileNetSSD_deploy.caffemodel \
--quantized_deploy_model /home/anhnt/CHaiDNN/tools/tools/MobileNet-SSD/models_quantd/MobileNetSSD_deploy_quantd.prototxt \
--calibration_directory /home/anhnt/CHaiDNN/tools/tools/JPEGImages/ \
--calibration_size 32 \
--bitwidths 8,8,8 --dims 3,300,300 --transpose 2,0,1 \
--channel_swap 2,1,0 --raw_scale 0.007843 \
--mean_value 1,1,1 --input_scale 1.0

but got error( hang run):

/usr/local/lib/python2.7/dist-packages/skimage/io/_io.py:49: UserWarning: `as_grey` has been deprecated in favor of `as_gray`
  warn('`as_grey` has been deprecated in favor of `as_gray`')
/usr/local/lib/python2.7/dist-packages/skimage/transform/_warps.py:105: UserWarning: The default mode, 'constant', will be changed to 'reflect' in skimage 0.15.
  warn("The default mode, 'constant', will be changed to 'reflect' in "
/usr/local/lib/python2.7/dist-packages/skimage/transform/_warps.py:110: UserWarning: Anti-aliasing will be enabled by default in skimage 0.15 to avoid aliasing artifacts when down-sampling images.
  warn("Anti-aliasing will be enabled by default in skimage 0.15 to "
quantize.py:33: RuntimeWarning: invalid value encountered in divide
  #     pass
quantize.py:33: RuntimeWarning: divide by zero encountered in log2
  #     pass

I quantized with params same the guide, but got accuracy very bad.
Please help me,
Thank you!

how can i nvme mount ?

I ran chaidnn using the zcu102 board.
For larger data, I'm trying to use an SSD, but the board does not recognize nvme.
I have verified that the lspci command recognizes ssd, but there is no nvme in / dev. Is there a way?

CHaiDNN on other boards

Dear all,

Has anyone tested CHaiDNN on other type of boards besides zcu102 and zcu104?
In particular I'm thinking on the possibility of using the light version of CHaiDNN (Diet CHaI) on low cost boards (such as the Zybo, Pynq ...). The idea would be using CNNs with very few layers, so presumably there should be enough hardware to handle that.

About SliceLayer

Do you have any plan or agenda to support SliceLayer?

Re-building designs results in timing error

Hi,

When I rebuild the reference designs, either from the scripts or in SDSOC 2017.4, the resulting implementation has timing violations. I find I need to set the speed of the hardware functions to 100MHz rather than the 200MHz in the instructions. Particularly for the scripts method, I do nothing more than run the instructions provided in the README file. Is this to be expected, or am I missing some extra step?

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