xilinx / resnet50-pynq

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

🚫 This repository has been archived. For up-to-date ResNet50 dataflow FPGA acceleration, please see FINN Examples.

Quantized ResNet50 Dataflow Acceleration on Alveo

This repository contains an implementations of a binary ResNet50 FINN-style dataflow accelerator targeting Alveo boards. It is intended as a showcase of achievable throughput and latency for ImageNet clasiffication on FPGA, using dataflow execution and on-chip weight storage.

Repo organization

The repository is organized as follows:

• src: contains source code and submodules
  • hls: HLS custom building blocks and submodules to FINN librares (FINN and FINN-HLSLib)
  • w1a2-v1.0: pre-build weights, thresholds, directives and configuration files for Binary ResNet50
• compile: contains scripts for accelerator compilation (Vivado HLS CSynth + Vivado Synthesis)
• link: contains scripts for accelerator linking into the Alveo platform with Vitis
• host: python and Jupyter host code, using PYNQ for Alveo

Building the Accelerator

The Accelerator is built using Vitis 2019.2. We recommend using this version, otherwise changes might be required to source and/or Makefiles for things to work.

To build the accelerator, clone the repository (using --recursive to pull submodules), after which:

cd ResNet50-PYNQ/compile
make NET=w1a2_v1.0
cd ../link
make

See the specific Compile and Link documentation for further info.

Running the Demo

After you have built the accelerator, you can install the required files in the host folder. Move in the cloned repo and do make install

cd ResNet50-PYNQ
make install

You can then run the included Jupyter notebook or the Python multithreaded inference example. If you want to use the distributed PYNQ python package, please read below. If you want to run example Python inference code, please see the host code documentation.

PYNQ quick start

Install the resnet50-pynq package using pip:

pip install resnet50-pynq

After the package is installed, to get your own copy of the available notebooks run:

pynq get-notebooks ResNet50

You can then try things out by doing:

cd pynq-notebooks
jupyter notebook

There are a number of additional options for the pynq get-notebooks command, you can list them by typing

pynq get-notebooks --help

You can also refer to the official PYNQ documentation for more information regarding the PYNQ Command Line Interface and in particular the get-notebooks command.

Supported Boards/Shells

Currently, we distribute the overlay only for the following Alveo boards and shells:

Shell	Board
xilinx_u250_xdma_201830_2	Xilinx Alveo U250

Designs are built using Vitis 2019.2.

Author

Lucian Petrica @ Xilinx Research Labs.

resnet50-pynq's Issues

Access to notebook on Pynq

Hi,
I wanted to run this on a Pynq-Z1 board and followed the "Pynq Quick Start" guidelines. However, after installing the python module successfully I can't get the notebook with the pynq get-notebooks ResNet50 command. It returns the following error:
ValueError: Notebooks modules 'ResNet50' not found. Make sure they exist and the source packages are installed.
Do you have any idea where the problem is coming from? Is there another way for me to get the notebook?
Hope you can help.

Alveo U200 - compile

Hi @quetric , @giunatale

Changed Makefile for Alveo U200 compilation . Please let me know, what are the changes required to generate overlay for U200.

Environment compatibility problems

Hello,
I am currently trying to run your project on my Alveo U250 board, but I am facing some issues. I noticed from trying to go through the notebook that the design needed xilinx-u250-xdma-201830.2 as shell on the board. However, after flashing this shell on the board using the last version of XRT and Ubuntu 20.04, the computer would not detect it anymore on the PCI port. I figured out it could be a compatibility problem so I tried using Ubuntu 18.04.5 instead. From this point, I am facing two issues:

• If I use XRT 2019.2, the board is detected my the lspci command, but not by the flash scan command from XRT, I therefore can't flash the bitstream onto the board.
• If I use XRT 2021.1, the board is found through flash scan, but isn't detected anymore anywhere after I put xilinx-u250-xdma-201830.2.

My request is the following: could you provide me the environment information you used for your project please? This would include your Linux kernel version (or distribution number) and the version of XRT you used.

Alternatively, could you point out to me what I would need to modify in your code to create a bitstream of the ResNet50 that would work with the last XDMA available?

Hoping you can help.

U250 compile errors

Hi, when I complied ur ResNet50 on U250. It cannot succeed, could you help me with that?

echo "Recipe for top layers"
Recipe for top layers
vivado_hls preres.tcl -tclargs xcu250-figd2104-2L-e w1a2_v1.0 ip > build_preres.log
cp build_preres/sol1/impl/ip/*.zip preres.zip
echo "Recipe for bottom layers"
Recipe for bottom layers
vivado_hls postres.tcl -tclargs xcu250-figd2104-2L-e w1a2_v1.0 ip > build_postres.log
cp build_postres/sol1/impl/ip/*.zip postres.zip
if [[ res2a = res*a ]]; then echo "Recipe for 2-branch block res2a"; else echo "Recipe for 1-branch block res2a"; fi
Recipe for 2-branch block res2a
rm -rf build_res2a
vivado_hls resblock.tcl -tclargs `if [[ res2a = res*a ]]; then echo 2; else echo 1; fi` res2a w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res2a.log
cp build_res2a/sol1/impl/ip/*.zip res2a.zip
if [[ res2b = res*a ]]; then echo "Recipe for 2-branch block res2b"; else echo "Recipe for 1-branch block res2b"; fi
Recipe for 1-branch block res2b
rm -rf build_res2b
vivado_hls resblock.tcl -tclargs `if [[ res2b = res*a ]]; then echo 2; else echo 1; fi` res2b w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res2b.log
cp build_res2b/sol1/impl/ip/*.zip res2b.zip
if [[ res2c = res*a ]]; then echo "Recipe for 2-branch block res2c"; else echo "Recipe for 1-branch block res2c"; fi
Recipe for 1-branch block res2c
rm -rf build_res2c
vivado_hls resblock.tcl -tclargs `if [[ res2c = res*a ]]; then echo 2; else echo 1; fi` res2c w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res2c.log
cp build_res2c/sol1/impl/ip/*.zip res2c.zip
if [[ res3a = res*a ]]; then echo "Recipe for 2-branch block res3a"; else echo "Recipe for 1-branch block res3a"; fi
Recipe for 2-branch block res3a
rm -rf build_res3a
vivado_hls resblock.tcl -tclargs `if [[ res3a = res*a ]]; then echo 2; else echo 1; fi` res3a w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res3a.log
cp build_res3a/sol1/impl/ip/*.zip res3a.zip
if [[ res3b = res*a ]]; then echo "Recipe for 2-branch block res3b"; else echo "Recipe for 1-branch block res3b"; fi
Recipe for 1-branch block res3b
rm -rf build_res3b
vivado_hls resblock.tcl -tclargs `if [[ res3b = res*a ]]; then echo 2; else echo 1; fi` res3b w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res3b.log
cp build_res3b/sol1/impl/ip/*.zip res3b.zip
if [[ res3c = res*a ]]; then echo "Recipe for 2-branch block res3c"; else echo "Recipe for 1-branch block res3c"; fi
Recipe for 1-branch block res3c
rm -rf build_res3c
vivado_hls resblock.tcl -tclargs `if [[ res3c = res*a ]]; then echo 2; else echo 1; fi` res3c w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res3c.log
cp build_res3c/sol1/impl/ip/*.zip res3c.zip
if [[ res3d = res*a ]]; then echo "Recipe for 2-branch block res3d"; else echo "Recipe for 1-branch block res3d"; fi
Recipe for 1-branch block res3d
rm -rf build_res3d
vivado_hls resblock.tcl -tclargs `if [[ res3d = res*a ]]; then echo 2; else echo 1; fi` res3d w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res3d.log
cp build_res3d/sol1/impl/ip/*.zip res3d.zip
if [[ res4a = res*a ]]; then echo "Recipe for 2-branch block res4a"; else echo "Recipe for 1-branch block res4a"; fi
Recipe for 2-branch block res4a
rm -rf build_res4a
vivado_hls resblock.tcl -tclargs `if [[ res4a = res*a ]]; then echo 2; else echo 1; fi` res4a w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res4a.log
cp build_res4a/sol1/impl/ip/*.zip res4a.zip
if [[ res4b = res*a ]]; then echo "Recipe for 2-branch block res4b"; else echo "Recipe for 1-branch block res4b"; fi
Recipe for 1-branch block res4b
rm -rf build_res4b
vivado_hls resblock.tcl -tclargs `if [[ res4b = res*a ]]; then echo 2; else echo 1; fi` res4b w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res4b.log
cp build_res4b/sol1/impl/ip/*.zip res4b.zip
if [[ res4c = res*a ]]; then echo "Recipe for 2-branch block res4c"; else echo "Recipe for 1-branch block res4c"; fi
Recipe for 1-branch block res4c
rm -rf build_res4c
vivado_hls resblock.tcl -tclargs `if [[ res4c = res*a ]]; then echo 2; else echo 1; fi` res4c w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res4c.log
cp build_res4c/sol1/impl/ip/*.zip res4c.zip
if [[ res4d = res*a ]]; then echo "Recipe for 2-branch block res4d"; else echo "Recipe for 1-branch block res4d"; fi
Recipe for 1-branch block res4d
rm -rf build_res4d
vivado_hls resblock.tcl -tclargs `if [[ res4d = res*a ]]; then echo 2; else echo 1; fi` res4d w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res4d.log
cp build_res4d/sol1/impl/ip/*.zip res4d.zip
if [[ res4e = res*a ]]; then echo "Recipe for 2-branch block res4e"; else echo "Recipe for 1-branch block res4e"; fi
Recipe for 1-branch block res4e
rm -rf build_res4e
vivado_hls resblock.tcl -tclargs `if [[ res4e = res*a ]]; then echo 2; else echo 1; fi` res4e w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res4e.log
cp build_res4e/sol1/impl/ip/*.zip res4e.zip
if [[ res4f = res*a ]]; then echo "Recipe for 2-branch block res4f"; else echo "Recipe for 1-branch block res4f"; fi
Recipe for 1-branch block res4f
rm -rf build_res4f
vivado_hls resblock.tcl -tclargs `if [[ res4f = res*a ]]; then echo 2; else echo 1; fi` res4f w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res4f.log
cp build_res4f/sol1/impl/ip/*.zip res4f.zip
if [[ res5a = res*a ]]; then echo "Recipe for 2-branch block res5a"; else echo "Recipe for 1-branch block res5a"; fi
Recipe for 2-branch block res5a
rm -rf build_res5a
vivado_hls resblock.tcl -tclargs `if [[ res5a = res*a ]]; then echo 2; else echo 1; fi` res5a w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res5a.log
cp build_res5a/sol1/impl/ip/*.zip res5a.zip
if [[ res5b = res*a ]]; then echo "Recipe for 2-branch block res5b"; else echo "Recipe for 1-branch block res5b"; fi
Recipe for 1-branch block res5b
rm -rf build_res5b
vivado_hls resblock.tcl -tclargs `if [[ res5b = res*a ]]; then echo 2; else echo 1; fi` res5b w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res5b.log
cp build_res5b/sol1/impl/ip/*.zip res5b.zip
if [[ res5c = res*a ]]; then echo "Recipe for 2-branch block res5c"; else echo "Recipe for 1-branch block res5c"; fi
Recipe for 1-branch block res5c
rm -rf build_res5c
vivado_hls resblock.tcl -tclargs `if [[ res5c = res*a ]]; then echo 2; else echo 1; fi` res5c w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res5c.log
cp build_res5c/sol1/impl/ip/*.zip res5c.zip
echo "Recipe for bidirectional DMA"
Recipe for bidirectional DMA
rm -rf build_inoutdma
vivado_hls inoutdma.tcl xcu250-figd2104-2L-e 4 w1a2_v1.0 ip > build_inoutdma.log
cp build_inoutdma/sol1/impl/ip/*.zip inoutdma.zip
vivado -mode batch -source ipi.tcl -tclargs 250 xcu250-figd2104-2L-e

****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source ipi.tcl
# set clkfreqmhz  [lindex $::argv 0]
# set device      [lindex $::argv 1]
# set origin_dir "."
# if { [info exists ::origin_dir_loc] } {
#   set origin_dir $::origin_dir_loc
# }
# set project_name "project_1"
# if { [info exists ::user_project_name] } {
#   set project_name $::user_project_name
# }
# variable script_file
# set script_file "ipi.tcl"
# proc help {} {
#   variable script_file
#   puts "\nDescription:"
#   puts "Recreate a Vivado project from this script. The created project will be"
#   puts "functionally equivalent to the original project for which this script was"
#   puts "generated. The script contains commands for creating a project, filesets,"
#   puts "runs, adding/importing sources and setting properties on various objects.\n"
#   puts "Syntax:"
#   puts "$script_file"
#   puts "$script_file -tclargs \[--origin_dir <path>\]"
#   puts "$script_file -tclargs \[--project_name <name>\]"
#   puts "$script_file -tclargs \[--help\]\n"
#   puts "Usage:"
#   puts "Name                   Description"
#   puts "-------------------------------------------------------------------------"
#   puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
#   puts "                       origin_dir path value is \".\", otherwise, the value"
#   puts "                       that was set with the \"-paths_relative_to\" switch"
#   puts "                       when this script was generated.\n"
#   puts "\[--project_name <name>\] Create project with the specified name. Default"
#   puts "                       name is the name of the project from where this"
#   puts "                       script was generated.\n"
#   puts "\[--help\]               Print help information for this script"
#   puts "-------------------------------------------------------------------------\n"
#   exit 0
# }
# if { $::argc > 0 } {
#   for {set i 0} {$i < [llength $::argc]} {incr i} {
#     set option [string trim [lindex $::argv $i]]
#     switch -regexp -- $option {
#       "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
#       "--project_name" { incr i; set project_name [lindex $::argv $i] }
#       "--help"         { help }
#       default {
#         if { [regexp {^-} $option] } {
#           puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
#           return 1
#         }
#       }
#     }
#   }
# }
# set orig_proj_dir "[file normalize "$origin_dir/project_1"]"
# create_project ${project_name} ./${project_name} -part ${device}
# set proj_dir [get_property directory [current_project]]
# set obj [current_project]
# set_property -name "part" -value "$device" -objects $obj
# set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
# set_property -name "dsa.num_compute_units" -value "60" -objects $obj
WARNING: [Common 17-599] Property 'dsa.num_compute_units' is deprecated for object type 'project'. dsa.* properties have been deprecated, please use the corresponding platform.* properties.
# set_property -name "ip_cache_permissions" -value "read write" -objects $obj
# set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj
# set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
# set_property -name "simulator_language" -value "Mixed" -objects $obj
# set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#   create_fileset -srcset sources_1
# }
# set obj [get_filesets sources_1]
# set_property "ip_repo_paths" "[file normalize "$origin_dir"]" $obj
# update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.2/data/ip'.
update_ip_catalog: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1579.117 ; gain = 59.656 ; free physical = 10770 ; free virtual = 13007
# set obj [get_filesets sources_1]
# set obj [get_filesets sources_1]
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#   create_fileset -constrset constrs_1
# }
# set obj [get_filesets constrs_1]
# set obj [get_filesets constrs_1]
# if {[string equal [get_filesets -quiet sim_1] ""]} {
#   create_fileset -simset sim_1
# }
# set obj [get_filesets sim_1]
# set obj [get_filesets sim_1]
# proc cr_bd_resnet50 { parentCell } {
# 
#   global clkfreqmhz
# 
#   # CHANGE DESIGN NAME HERE
#   set design_name resnet50
# 
#   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
# 
#   create_bd_design $design_name
# 
#   set bCheckIPsPassed 1
#   ##################################################################
#   # CHECK IPs
#   ##################################################################
#   set bCheckIPs 1
#   if { $bCheckIPs == 1 } {
#      set list_check_ips "\ 
#   xilinx.com:hls:res2a:1.0\
#   xilinx.com:hls:res2b:1.0\
#   xilinx.com:hls:res2c:1.0\
#   xilinx.com:hls:res3a:1.0\
#   xilinx.com:hls:res3b:1.0\
#   xilinx.com:hls:res3c:1.0\
#   xilinx.com:hls:res3d:1.0\
#   xilinx.com:hls:res4a:1.0\
#   xilinx.com:hls:res4b:1.0\
#   xilinx.com:hls:res4c:1.0\
#   xilinx.com:hls:res4d:1.0\
#   xilinx.com:hls:res4e:1.0\
#   xilinx.com:hls:res4f:1.0\
#   xilinx.com:hls:res5a:1.0\
#   xilinx.com:hls:res5b:1.0\
#   xilinx.com:hls:res5c:1.0\
#   xilinx.com:hls:inoutdma:1.0\
#   xilinx.com:hls:preres:1.0\
#   xilinx.com:hls:postres:1.0\
#   "
# 
#    set list_ips_missing ""
#    common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
# 
#    foreach ip_vlnv $list_check_ips {
#       set ip_obj [get_ipdefs -all $ip_vlnv]
#       if { $ip_obj eq "" } {
#          lappend list_ips_missing $ip_vlnv
#       }
#    }
# 
#    if { $list_ips_missing ne "" } {
#       catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
#       set bCheckIPsPassed 0
#    }
# 
#   }
# 
#   if { $bCheckIPsPassed != 1 } {
#     common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
#     return 3
#   }
# 
#   variable script_folder
# 
#   if { $parentCell eq "" } {
#      set parentCell [get_bd_cells /]
#   }
# 
#   # Get object for parentCell
#   set parentObj [get_bd_cells $parentCell]
#   if { $parentObj == "" } {
#      catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
#      return
#   }
# 
#   # Make sure parentObj is hier blk
#   set parentType [get_property TYPE $parentObj]
#   if { $parentType ne "hier" } {
#      catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
#      return
#   }
# 
#   # Save current instance; Restore later
#   set oldCurInst [current_bd_instance .]
# 
#   # Set parent object as current
#   current_bd_instance $parentObj
# 
#   # Create clock and reset ports according to SDx spec
#   create_bd_port -dir I -type clk ap_clk
#   set_property CONFIG.FREQ_HZ [expr {$clkfreqmhz*1000000}] [get_bd_ports ap_clk]
#   create_bd_port -dir I -type rst ap_rst_n
#   set_property CONFIG.POLARITY ACTIVE_LOW [get_bd_ports ap_rst_n]
# 
#   # Create resblock instances
#   set res2a_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res2a:1.0 res2a_0 ]
#   set res2b_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res2b:1.0 res2b_0 ]
#   set res2c_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res2c:1.0 res2c_0 ]
#   set res3a_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res3a:1.0 res3a_0 ]
#   set res3b_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res3b:1.0 res3b_0 ]
#   set res3c_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res3c:1.0 res3c_0 ]
#   set res3d_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res3d:1.0 res3d_0 ]
#   set res4a_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res4a:1.0 res4a_0 ]
#   set res4b_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res4b:1.0 res4b_0 ]
#   set res4c_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res4c:1.0 res4c_0 ]
#   set res4d_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res4d:1.0 res4d_0 ]
#   set res4e_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res4e:1.0 res4e_0 ]
#   set res4f_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res4f:1.0 res4f_0 ]
#   set res5a_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res5a:1.0 res5a_0 ]
#   set res5b_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res5b:1.0 res5b_0 ]
#   set res5c_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:res5c:1.0 res5c_0 ]
# 
#   set inoutdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:inoutdma:1.0 inoutdma_0 ]
#   set preres_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:preres:1.0 preres_0 ]
#   set postres_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:postres:1.0 postres_0 ]
# 
#   #create reset infrastructure
#   #reset originates in SLR0 and we pipeline it using one register in each slr:
#   #SLR0 -> SLR1 -> SLR2 -> SLR3
#   #from each slr pipeline register, we push the reset through a BUFG to destinations
#   #using a passthrough reduced logic to avoid wire type errors 
#   foreach RST [list 0] {
#     foreach SLR [list 0 1 2 3] {
#       puts "Implementing reset ${RST} infrastructure for SLR${SLR}"
# 
#       create_bd_cell -type ip -vlnv xilinx.com:ip:c_shift_ram:12.0 rst${RST}_pipe_slr${SLR}
#       set_property -dict [list CONFIG.Width.VALUE_SRC USER] [get_bd_cells rst${RST}_pipe_slr${SLR}]
#       set_property -dict [list CONFIG.Width {1} CONFIG.Depth {1} CONFIG.DefaultData {0} CONFIG.AsyncInitVal {0} CONFIG.SSET {false} CONFIG.SCLR {false} CONFIG.SyncInitVal {0}] [get_bd_cells rst${RST}_pipe_slr${SLR}]
#       if {$RST == 0} {
#         connect_bd_net [get_bd_ports ap_clk] [get_bd_pins rst${RST}_pipe_slr${SLR}/CLK]
#       } else {
#         connect_bd_net [get_bd_ports ap_clk_2] [get_bd_pins rst${RST}_pipe_slr${SLR}/CLK]
#       }
#       if {$SLR == 0} {
#         #one passthrough to remove reset attribute from net
#         create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 rst${RST}_conv_in
#         set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {or}] [get_bd_cells rst${RST}_conv_in]
#         if {$RST == 0} {
#           connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins rst${RST}_conv_in/Op1]
#         } else {
#           connect_bd_net [get_bd_ports ap_rst_n_2] [get_bd_pins rst${RST}_conv_in/Op1]
#         }
#         connect_bd_net [get_bd_pins rst${RST}_conv_in/Res] [get_bd_pins rst${RST}_pipe_slr${SLR}/D]
#       } else {
#         connect_bd_net [get_bd_pins rst${RST}_pipe_slr[expr {$SLR-1}]/Q] [get_bd_pins rst${RST}_pipe_slr${SLR}/D]
#       }
#       create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rst${RST}_buf_slr${SLR}
#       set_property -dict [list CONFIG.C_BUF_TYPE {BUFG}] [get_bd_cells rst${RST}_buf_slr${SLR}]
#       connect_bd_net [get_bd_pins rst${RST}_pipe_slr${SLR}/Q] [get_bd_pins rst${RST}_buf_slr${SLR}/BUFG_I]
# 
#       create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 rst${RST}_pass_slr${SLR}
#       set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {or}] [get_bd_cells rst${RST}_pass_slr${SLR}]
#       connect_bd_net [get_bd_pins rst${RST}_buf_slr${SLR}/BUFG_O] [get_bd_pins rst${RST}_pass_slr${SLR}/Op1]
#     }
#   }
# 
#   save_bd_design
# 
#   # Make AXI interfaces external and rename them to standard names
#   make_bd_intf_pins_external  [get_bd_intf_pins inoutdma_0/m_axi_gmem0]
#   make_bd_intf_pins_external  [get_bd_intf_pins inoutdma_0/m_axi_gmem1]
#   make_bd_intf_pins_external  [get_bd_intf_pins inoutdma_0/m_axi_gmem2]
#   make_bd_intf_pins_external  [get_bd_intf_pins inoutdma_0/s_axi_control]
#   set_property name m_axi_gmem0 [get_bd_intf_ports m_axi_gmem0_0]
#   set_property name m_axi_gmem1 [get_bd_intf_ports m_axi_gmem1_0]
#   set_property name m_axi_gmem2 [get_bd_intf_ports m_axi_gmem2_0]
#   set_property name s_axi_control [get_bd_intf_ports s_axi_control_0]
# 
#   # Create port connections
#   connect_bd_net [get_bd_ports ap_clk] [get_bd_pins res2a_0/ap_clk] [get_bd_pins res2b_0/ap_clk] [get_bd_pins res2c_0/ap_clk] [get_bd_pins res3a_0/ap_clk] [get_bd_pins res3b_0/ap_clk] [get_bd_pins res3c_0/ap_clk] [get_bd_pins res3d_0/ap_clk] [get_bd_pins res4a_0/ap_clk] [get_bd_pins res4b_0/ap_clk] [get_bd_pins res4c_0/ap_clk] [get_bd_pins res4d_0/ap_clk] [get_bd_pins res4e_0/ap_clk] [get_bd_pins res4f_0/ap_clk] [get_bd_pins res5a_0/ap_clk] [get_bd_pins res5b_0/ap_clk] [get_bd_pins res5c_0/ap_clk] [get_bd_pins inoutdma_0/ap_clk] [get_bd_pins preres_0/ap_clk] [get_bd_pins postres_0/ap_clk]
#   connect_bd_net [get_bd_pins rst0_pass_slr0/Res] [get_bd_pins res3d_0/ap_rst_n] [get_bd_pins inoutdma_0/ap_rst_n] [get_bd_pins preres_0/ap_rst_n] [get_bd_pins postres_0/ap_rst_n]
#   connect_bd_net [get_bd_pins rst0_pass_slr1/Res] [get_bd_pins res2a_0/ap_rst_n] [get_bd_pins res3c_0/ap_rst_n] [get_bd_pins res4a_0/ap_rst_n] [get_bd_pins res4b_0/ap_rst_n] [get_bd_pins res5c_0/ap_rst_n]
#   connect_bd_net [get_bd_pins rst0_pass_slr2/Res] [get_bd_pins res2b_0/ap_rst_n] [get_bd_pins res3b_0/ap_rst_n] [get_bd_pins res4c_0/ap_rst_n] [get_bd_pins res4d_0/ap_rst_n] [get_bd_pins res5b_0/ap_rst_n]
#   connect_bd_net [get_bd_pins rst0_pass_slr3/Res] [get_bd_pins res2c_0/ap_rst_n] [get_bd_pins res3a_0/ap_rst_n] [get_bd_pins res4e_0/ap_rst_n] [get_bd_pins res4f_0/ap_rst_n] [get_bd_pins res5a_0/ap_rst_n]
# 
#   foreach SRC [list inoutdma preres res2a res2b res2c res3a res3b res3c res3d res4a res4b res4c res4d res4e res4f res5a res5b res5c postres] DST [list preres res2a res2b res2c res3a res3b res3c res3d res4a res4b res4c res4d res4e res4f res5a res5b res5c postres inoutdma] {
#     set OUTWB [get_property [list CONFIG.TDATA_NUM_BYTES] [get_bd_intf_pins ${SRC}_0/output_V_V]]
#     set INWB [get_property [list CONFIG.TDATA_NUM_BYTES] [get_bd_intf_pins ${DST}_0/input_V_V]]
#     if {$OUTWB != $INWB} {
#       puts "Connecting $SRC to $DST through FIFOs and data width converter: $SRC -> FIFO -> DWC(${OUTWB}B -> ${INWB}B) -> FIFO -> $DST"
#       create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 dwc_${SRC}_${DST}
#       set_property -dict [list CONFIG.S_TDATA_NUM_BYTES $OUTWB] [get_bd_cells dwc_${SRC}_${DST}]
#       set_property -dict [list CONFIG.M_TDATA_NUM_BYTES $INWB] [get_bd_cells dwc_${SRC}_${DST}]
# 
#       create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 fifo_${SRC}_dwc
#       set_property -dict [list CONFIG.FIFO_DEPTH {1024} CONFIG.IS_ACLK_ASYNC {0} CONFIG.FIFO_MEMORY_TYPE {ultra}] [get_bd_cells fifo_${SRC}_dwc]
#       connect_bd_net [get_bd_ports ap_clk] [get_bd_pins fifo_${SRC}_dwc/s_axis_aclk]
#       connect_bd_net [get_bd_pins ${SRC}_0/ap_rst_n] [get_bd_pins fifo_${SRC}_dwc/s_axis_aresetn]
#       connect_bd_intf_net [get_bd_intf_pins ${SRC}_0/output_V_V] [get_bd_intf_pins fifo_${SRC}_dwc/S_AXIS]
#       connect_bd_intf_net [get_bd_intf_pins fifo_${SRC}_dwc/M_AXIS] [get_bd_intf_pins dwc_${SRC}_${DST}/S_AXIS]
# 
#       create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 fifo_dwc_${DST}
#       set_property -dict [list CONFIG.FIFO_DEPTH {1024} CONFIG.IS_ACLK_ASYNC {0} CONFIG.FIFO_MEMORY_TYPE {ultra}] [get_bd_cells fifo_dwc_${DST}]
#       connect_bd_net [get_bd_ports ap_clk] [get_bd_pins fifo_dwc_${DST}/s_axis_aclk]
#       connect_bd_net [get_bd_pins ${SRC}_0/ap_rst_n] [get_bd_pins fifo_dwc_${DST}/s_axis_aresetn]
#       connect_bd_intf_net [get_bd_intf_pins dwc_${SRC}_${DST}/M_AXIS] [get_bd_intf_pins fifo_dwc_${DST}/S_AXIS]
#       connect_bd_intf_net [get_bd_intf_pins fifo_dwc_${DST}/M_AXIS] [get_bd_intf_pins ${DST}_0/input_V_V]
# 
#       connect_bd_net [get_bd_ports ap_clk] [get_bd_pins dwc_${SRC}_${DST}/aclk]
#       connect_bd_net [get_bd_pins ${SRC}_0/ap_rst_n] [get_bd_pins dwc_${SRC}_${DST}/aresetn]
#     } else {
#       puts "Connecting $SRC to $DST through FIFO: $SRC -> FIFO -> $DST"
#       create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 fifo_${SRC}_${DST}
#       set_property -dict [list CONFIG.FIFO_DEPTH {1024} CONFIG.IS_ACLK_ASYNC {0} CONFIG.FIFO_MEMORY_TYPE {ultra}] [get_bd_cells fifo_${SRC}_${DST}]
#       connect_bd_net [get_bd_ports ap_clk] [get_bd_pins fifo_${SRC}_${DST}/s_axis_aclk]
#       connect_bd_net [get_bd_pins ${SRC}_0/ap_rst_n] [get_bd_pins fifo_${SRC}_${DST}/s_axis_aresetn]
#       connect_bd_intf_net [get_bd_intf_pins ${SRC}_0/output_V_V] [get_bd_intf_pins fifo_${SRC}_${DST}/S_AXIS]
#       connect_bd_intf_net [get_bd_intf_pins fifo_${SRC}_${DST}/M_AXIS] [get_bd_intf_pins ${DST}_0/input_V_V]
#     }
#   }
#   connect_bd_intf_net [get_bd_intf_pins inoutdma_0/weights_V_V] [get_bd_intf_pins postres_0/weights_V_V]
# 
#   # Auto-assign addresses (TODO: check)
#   exclude_bd_addr_seg [get_bd_addr_segs inoutdma_0/Data_m_axi_gmem0/SEG_m_axi_gmem0_Reg]
#   exclude_bd_addr_seg [get_bd_addr_segs inoutdma_0/Data_m_axi_gmem1/SEG_m_axi_gmem1_Reg]
#   exclude_bd_addr_seg [get_bd_addr_segs inoutdma_0/Data_m_axi_gmem2/SEG_m_axi_gmem2_Reg]
#   exclude_bd_addr_seg [get_bd_addr_segs s_axi_control/SEG_inoutdma_0_Reg]
# 
#   # Restore current instance
#   current_bd_instance $oldCurInst
# 
#   save_bd_design
#   close_bd_design $design_name 
# }
# cr_bd_resnet50 ""
INFO: [BD_TCL-3] Currently there is no design <resnet50> in project, so creating one...
Wrote  : </home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/resnet50.bd> 
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog:  
  xilinx.com:hls:res2a:1.0 xilinx.com:hls:res2b:1.0 xilinx.com:hls:res2c:1.0 xilinx.com:hls:res3a:1.0 xilinx.com:hls:res3b:1.0 xilinx.com:hls:res3c:1.0 xilinx.com:hls:res3d:1.0 xilinx.com:hls:res4a:1.0 xilinx.com:hls:res4b:1.0 xilinx.com:hls:res4c:1.0 xilinx.com:hls:res4d:1.0 xilinx.com:hls:res4e:1.0 xilinx.com:hls:res4f:1.0 xilinx.com:hls:res5a:1.0 xilinx.com:hls:res5b:1.0 xilinx.com:hls:res5c:1.0 xilinx.com:hls:inoutdma:1.0 xilinx.com:hls:preres:1.0 xilinx.com:hls:postres:1.0  .
WARNING: [BD 5-670] It is required to provide a frequency value for a user created input clock port. Please use the <-freq_hz $freq_val> argument of the create_bd_port command. ie create_bd_port -dir I -type clk -freq_hz 100000000 clkin
Implementing reset 0 infrastructure for SLR0
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr0/Q(data) and /rst0_buf_slr0/BUFG_I(clk)
Implementing reset 0 infrastructure for SLR1
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr1/Q(data) and /rst0_buf_slr1/BUFG_I(clk)
Implementing reset 0 infrastructure for SLR2
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr2/Q(data) and /rst0_buf_slr2/BUFG_I(clk)
Implementing reset 0 infrastructure for SLR3
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr3/Q(data) and /rst0_buf_slr3/BUFG_I(clk)
Wrote  : </home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/resnet50.bd> 
Connecting inoutdma to preres through FIFOs and data width converter: inoutdma -> FIFO -> DWC(64B -> 3B) -> FIFO -> preres
Connecting preres to res2a through FIFOs and data width converter: preres -> FIFO -> DWC(16B -> 8B) -> FIFO -> res2a
Connecting res2a to res2b through FIFO: res2a -> FIFO -> res2b
Connecting res2b to res2c through FIFO: res2b -> FIFO -> res2c
Connecting res2c to res3a through FIFO: res2c -> FIFO -> res3a
Connecting res3a to res3b through FIFO: res3a -> FIFO -> res3b
Connecting res3b to res3c through FIFO: res3b -> FIFO -> res3c
Connecting res3c to res3d through FIFO: res3c -> FIFO -> res3d
Connecting res3d to res4a through FIFO: res3d -> FIFO -> res4a
Connecting res4a to res4b through FIFO: res4a -> FIFO -> res4b
Connecting res4b to res4c through FIFO: res4b -> FIFO -> res4c
Connecting res4c to res4d through FIFO: res4c -> FIFO -> res4d
Connecting res4d to res4e through FIFO: res4d -> FIFO -> res4e
Connecting res4e to res4f through FIFO: res4e -> FIFO -> res4f
Connecting res4f to res5a through FIFO: res4f -> FIFO -> res5a
Connecting res5a to res5b through FIFO: res5a -> FIFO -> res5b
Connecting res5b to res5c through FIFO: res5b -> FIFO -> res5c
Connecting res5c to postres through FIFO: res5c -> FIFO -> postres
Connecting postres to inoutdma through FIFO: postres -> FIFO -> inoutdma
Wrote  : </home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/resnet50.bd> 
# set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [ get_files resnet50.bd ] 
# make_wrapper -files [get_files resnet50.bd] -import -fileset sources_1 -top
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr0/Q(data) and /rst0_buf_slr0/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr1/Q(data) and /rst0_buf_slr1/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr2/Q(data) and /rst0_buf_slr2/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr3/Q(data) and /rst0_buf_slr3/BUFG_I(clk)
CRITICAL WARNING: [BD 41-1356] Slave segment </inoutdma_0/s_axi_control/Reg> is not assigned into address space </s_axi_control>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem0/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem0>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem1/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem1>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem2/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem2>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </inoutdma_0/s_axi_control/Reg> is not assigned into address space </s_axi_control>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem0/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem0>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem1/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem1>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem2/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem2>. Please use Address Editor to either assign or exclude it.
INFO: [xilinx.com:ip:c_shift_ram:12.0-913] /rst0_pipe_slr2 Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_shift_ram:12.0-913] /rst0_pipe_slr3 Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_shift_ram:12.0-913] /rst0_pipe_slr0 Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_shift_ram:12.0-913] /rst0_pipe_slr1 Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
Wrote  : </home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/resnet50.bd> 
VHDL Output written to : /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/synth/resnet50.v
VHDL Output written to : /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/sim/resnet50.v
VHDL Output written to : /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/hdl/resnet50_wrapper.v
WARNING: [Vivado 12-3482] The generated wrapper file has already been imported into the project, the imported file is:
'/home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/imports/hdl/resnet50_wrapper.v'
# set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]
# launch_runs synth_1 -jobs 10
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr0/Q(data) and /rst0_buf_slr0/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr1/Q(data) and /rst0_buf_slr1/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr2/Q(data) and /rst0_buf_slr2/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /rst0_pipe_slr3/Q(data) and /rst0_buf_slr3/BUFG_I(clk)
INFO: [BD 41-1662] The design 'resnet50.bd' is already validated. Therefore parameter propagation will not be re-run.
CRITICAL WARNING: [BD 41-1356] Slave segment </inoutdma_0/s_axi_control/Reg> is not assigned into address space </s_axi_control>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem0/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem0>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem1/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem1>. Please use Address Editor to either assign or exclude it.
CRITICAL WARNING: [BD 41-1356] Slave segment </m_axi_gmem2/Reg> is not assigned into address space </inoutdma_0/Data_m_axi_gmem2>. Please use Address Editor to either assign or exclude it.
VHDL Output written to : /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/synth/resnet50.v
VHDL Output written to : /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/sim/resnet50.v
VHDL Output written to : /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/hdl/resnet50_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block res2a_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res2b_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res2c_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res3a_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res3b_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res3c_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res3d_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res4a_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res4b_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res4c_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res4d_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res4e_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res4f_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res5a_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res5b_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block res5c_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block inoutdma_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block preres_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block postres_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_pipe_slr0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_conv_in .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_buf_slr0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_pass_slr0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_pipe_slr1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_buf_slr1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_pass_slr1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_pipe_slr2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_buf_slr2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_pass_slr2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_pipe_slr3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_buf_slr3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst0_pass_slr3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dwc_inoutdma_preres .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_inoutdma_dwc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_dwc_preres .
INFO: [BD 41-1029] Generation completed for the IP Integrator block dwc_preres_res2a .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_preres_dwc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_dwc_res2a .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res2a_res2b .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res2b_res2c .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res2c_res3a .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res3a_res3b .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res3b_res3c .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res3c_res3d .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res3d_res4a .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res4a_res4b .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res4b_res4c .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res4c_res4d .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res4d_res4e .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res4e_res4f .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res4f_res5a .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res5a_res5b .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res5b_res5c .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_res5c_postres .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_postres_inoutdma .
Exporting to file /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/hw_handoff/resnet50.hwh
Generated Block Design Tcl file /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/hw_handoff/resnet50_bd.tcl
Generated Hardware Definition File /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.srcs/sources_1/bd/resnet50/synth/resnet50.hwdef
INFO: [IP_Flow 19-5642] Done with IP cache export for multiple IPs
[Fri Nov 19 04:28:04 2021] Launched resnet50_res4c_0_0_synth_1, resnet50_res4d_0_0_synth_1, resnet50_res3b_0_0_synth_1, resnet50_res3a_0_0_synth_1, resnet50_res2c_0_0_synth_1, resnet50_res2b_0_0_synth_1, resnet50_res3d_0_0_synth_1, resnet50_res3c_0_0_synth_1, resnet50_res2a_0_0_synth_1, resnet50_res4a_0_0_synth_1, resnet50_res4b_0_0_synth_1, resnet50_rst0_pipe_slr3_0_synth_1, resnet50_rst0_buf_slr3_0_synth_1, resnet50_rst0_pass_slr3_0_synth_1, resnet50_dwc_inoutdma_preres_0_synth_1, resnet50_fifo_inoutdma_dwc_0_synth_1, resnet50_fifo_dwc_preres_0_synth_1, resnet50_dwc_preres_res2a_0_synth_1, resnet50_fifo_preres_dwc_0_synth_1, resnet50_fifo_dwc_res2a_0_synth_1, resnet50_fifo_res2a_res2b_0_synth_1, resnet50_fifo_res2b_res2c_0_synth_1, resnet50_fifo_res2c_res3a_0_synth_1, resnet50_fifo_res3a_res3b_0_synth_1, resnet50_fifo_res3b_res3c_0_synth_1, resnet50_fifo_res3c_res3d_0_synth_1, resnet50_fifo_res3d_res4a_0_synth_1, resnet50_fifo_res4a_res4b_0_synth_1, resnet50_fifo_res4b_res4c_0_synth_1, resnet50_fifo_res4c_res4d_0_synth_1, resnet50_fifo_res4d_res4e_0_synth_1, resnet50_fifo_res4e_res4f_0_synth_1, resnet50_fifo_res4f_res5a_0_synth_1, resnet50_fifo_res5a_res5b_0_synth_1, resnet50_fifo_res5b_res5c_0_synth_1, resnet50_fifo_res5c_postres_0_synth_1, resnet50_fifo_postres_inoutdma_0_synth_1, resnet50_res4e_0_0_synth_1, resnet50_res4f_0_0_synth_1, resnet50_res5a_0_0_synth_1, resnet50_res5b_0_0_synth_1, resnet50_res5c_0_0_synth_1, resnet50_inoutdma_0_0_synth_1, resnet50_preres_0_0_synth_1, resnet50_postres_0_0_synth_1, resnet50_rst0_pipe_slr0_0_synth_1, resnet50_rst0_conv_in_0_synth_1, resnet50_rst0_buf_slr0_0_synth_1, resnet50_rst0_pass_slr0_0_synth_1, resnet50_rst0_pipe_slr1_0_synth_1, resnet50_rst0_buf_slr1_0_synth_1, resnet50_rst0_pass_slr1_0_synth_1, resnet50_rst0_pipe_slr2_0_synth_1, resnet50_rst0_buf_slr2_0_synth_1, resnet50_rst0_pass_slr2_0_synth_1...
Run output will be captured here:
resnet50_res4c_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res4c_0_0_synth_1/runme.log
resnet50_res4d_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res4d_0_0_synth_1/runme.log
resnet50_res3b_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res3b_0_0_synth_1/runme.log
resnet50_res3a_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res3a_0_0_synth_1/runme.log
resnet50_res2c_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res2c_0_0_synth_1/runme.log
resnet50_res2b_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res2b_0_0_synth_1/runme.log
resnet50_res3d_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res3d_0_0_synth_1/runme.log
resnet50_res3c_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res3c_0_0_synth_1/runme.log
resnet50_res2a_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res2a_0_0_synth_1/runme.log
resnet50_res4a_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res4a_0_0_synth_1/runme.log
resnet50_res4b_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res4b_0_0_synth_1/runme.log
resnet50_rst0_pipe_slr3_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_pipe_slr3_0_synth_1/runme.log
resnet50_rst0_buf_slr3_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_buf_slr3_0_synth_1/runme.log
resnet50_rst0_pass_slr3_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_pass_slr3_0_synth_1/runme.log
resnet50_dwc_inoutdma_preres_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_dwc_inoutdma_preres_0_synth_1/runme.log
resnet50_fifo_inoutdma_dwc_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_inoutdma_dwc_0_synth_1/runme.log
resnet50_fifo_dwc_preres_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_dwc_preres_0_synth_1/runme.log
resnet50_dwc_preres_res2a_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_dwc_preres_res2a_0_synth_1/runme.log
resnet50_fifo_preres_dwc_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_preres_dwc_0_synth_1/runme.log
resnet50_fifo_dwc_res2a_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_dwc_res2a_0_synth_1/runme.log
resnet50_fifo_res2a_res2b_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res2a_res2b_0_synth_1/runme.log
resnet50_fifo_res2b_res2c_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res2b_res2c_0_synth_1/runme.log
resnet50_fifo_res2c_res3a_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res2c_res3a_0_synth_1/runme.log
resnet50_fifo_res3a_res3b_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res3a_res3b_0_synth_1/runme.log
resnet50_fifo_res3b_res3c_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res3b_res3c_0_synth_1/runme.log
resnet50_fifo_res3c_res3d_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res3c_res3d_0_synth_1/runme.log
resnet50_fifo_res3d_res4a_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res3d_res4a_0_synth_1/runme.log
resnet50_fifo_res4a_res4b_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res4a_res4b_0_synth_1/runme.log
resnet50_fifo_res4b_res4c_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res4b_res4c_0_synth_1/runme.log
resnet50_fifo_res4c_res4d_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res4c_res4d_0_synth_1/runme.log
resnet50_fifo_res4d_res4e_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res4d_res4e_0_synth_1/runme.log
resnet50_fifo_res4e_res4f_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res4e_res4f_0_synth_1/runme.log
resnet50_fifo_res4f_res5a_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res4f_res5a_0_synth_1/runme.log
resnet50_fifo_res5a_res5b_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res5a_res5b_0_synth_1/runme.log
resnet50_fifo_res5b_res5c_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res5b_res5c_0_synth_1/runme.log
resnet50_fifo_res5c_postres_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_res5c_postres_0_synth_1/runme.log
resnet50_fifo_postres_inoutdma_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_fifo_postres_inoutdma_0_synth_1/runme.log
resnet50_res4e_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res4e_0_0_synth_1/runme.log
resnet50_res4f_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res4f_0_0_synth_1/runme.log
resnet50_res5a_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res5a_0_0_synth_1/runme.log
resnet50_res5b_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res5b_0_0_synth_1/runme.log
resnet50_res5c_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_res5c_0_0_synth_1/runme.log
resnet50_inoutdma_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_inoutdma_0_0_synth_1/runme.log
resnet50_preres_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_preres_0_0_synth_1/runme.log
resnet50_postres_0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_postres_0_0_synth_1/runme.log
resnet50_rst0_pipe_slr0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_pipe_slr0_0_synth_1/runme.log
resnet50_rst0_conv_in_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_conv_in_0_synth_1/runme.log
resnet50_rst0_buf_slr0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_buf_slr0_0_synth_1/runme.log
resnet50_rst0_pass_slr0_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_pass_slr0_0_synth_1/runme.log
resnet50_rst0_pipe_slr1_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_pipe_slr1_0_synth_1/runme.log
resnet50_rst0_buf_slr1_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_buf_slr1_0_synth_1/runme.log
resnet50_rst0_pass_slr1_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_pass_slr1_0_synth_1/runme.log
resnet50_rst0_pipe_slr2_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_pipe_slr2_0_synth_1/runme.log
resnet50_rst0_buf_slr2_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_buf_slr2_0_synth_1/runme.log
resnet50_rst0_pass_slr2_0_synth_1: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/resnet50_rst0_pass_slr2_0_synth_1/runme.log
[Fri Nov 19 04:28:04 2021] Launched synth_1...
Run output will be captured here: /home/enai/Desktop/project/enai0/ResNet50-PYNQ/compile/project_1/project_1.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2873.160 ; gain = 1009.547 ; free physical = 9734 ; free virtual = 12438
# wait_on_run [get_runs synth_1]
[Fri Nov 19 04:28:04 2021] Waiting for synth_1 to finish...
[Fri Nov 19 04:47:16 2021] synth_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'resnet50_res4c_0_0_synth_1', 'resnet50_res4d_0_0_synth_1', 'resnet50_res3b_0_0_synth_1', 'resnet50_res3a_0_0_synth_1', 'resnet50_res2c_0_0_synth_1', 'resnet50_res2b_0_0_synth_1', 'resnet50_res3d_0_0_synth_1', 'resnet50_res3c_0_0_synth_1', 'resnet50_res2a_0_0_synth_1', 'resnet50_res4a_0_0_synth_1', 'resnet50_res4b_0_0_synth_1', 'resnet50_rst0_pipe_slr3_0_synth_1', 'resnet50_rst0_buf_slr3_0_synth_1', 'resnet50_rst0_pass_slr3_0_synth_1', 'resnet50_dwc_inoutdma_preres_0_synth_1', 'resnet50_fifo_inoutdma_dwc_0_synth_1', 'resnet50_fifo_dwc_preres_0_synth_1', 'resnet50_dwc_preres_res2a_0_synth_1', 'resnet50_fifo_preres_dwc_0_synth_1', 'resnet50_fifo_dwc_res2a_0_synth_1', 'resnet50_fifo_res2a_res2b_0_synth_1', 'resnet50_fifo_res2b_res2c_0_synth_1', 'resnet50_fifo_res2c_res3a_0_synth_1', 'resnet50_fifo_res3a_res3b_0_synth_1', 'resnet50_fifo_res3b_res3c_0_synth_1', 'resnet50_fifo_res3c_res3d_0_synth_1', 'resnet50_fifo_res3d_res4a_0_synth_1', 'resnet50_fifo_res4a_res4b_0_synth_1', 'resnet50_fifo_res4b_res4c_0_synth_1', 'resnet50_fifo_res4c_res4d_0_synth_1', 'resnet50_fifo_res4d_res4e_0_synth_1', 'resnet50_fifo_res4e_res4f_0_synth_1', 'resnet50_fifo_res4f_res5a_0_synth_1', 'resnet50_fifo_res5a_res5b_0_synth_1', 'resnet50_fifo_res5b_res5c_0_synth_1', 'resnet50_fifo_postres_inoutdma_0_synth_1', 'resnet50_res4e_0_0_synth_1', 'resnet50_res4f_0_0_synth_1', 'resnet50_res5a_0_0_synth_1', 'resnet50_res5b_0_0_synth_1', 'resnet50_res5c_0_0_synth_1', 'resnet50_inoutdma_0_0_synth_1', 'resnet50_preres_0_0_synth_1', 'resnet50_rst0_conv_in_0_synth_1', 'resnet50_rst0_pass_slr1_0_synth_1'
wait_on_run: Time (s): cpu = 00:00:03 ; elapsed = 00:19:13 . Memory (MB): peak = 2873.160 ; gain = 0.000 ; free physical = 170 ; free virtual = 793
# set ipdir $origin_dir/ip
# if {[file exists $ipdir]} {
#     file delete -force $ipdir
# }
# file mkdir $ipdir
# open_run synth_1 -name synth_1
ERROR: [Common 17-69] Command failed: Run 'synth_1' has not been launched. Unable to open
INFO: [Common 17-206] Exiting Vivado at Fri Nov 19 04:47:16 2021...
Makefile:45: recipe for target 'resnet50.xo' failed

@quetric @stsoe @

Use PLRAM for FC weights

Store the 2 MBytes of weights of the fully connected layer on-chip in URAM using the PLRAM mechanism. This should reduce power and increase throughput by reducing the total load on external DDR.

Make failed for U250

I made test on my local host step by step with instruction, when execute "make NET=w1a2_v1.0", it comes some error.

if [[ res2a = res*a ]]; then echo "Recipe for 2-branch block res2a"; else echo "Recipe for 1-branch block res2a"; fi
/bin/sh: 1: [[: not found
Recipe for 1-branch block res2a
rm -rf build_res2a
vivado_hls resblock.tcl -tclargs `if [[ res2a = res*a ]]; then echo 2; else echo 1; fi` res2a w1a2_v1.0 ip xcu250-figd2104-2L-e > build_res2a.log
/bin/sh: 1: [[: not found
Makefile:50: recipe for target 'res2a.zip' failed
make: *** [res2a.zip] Error 1

And I checked the log file build_res2a.log, there is some error in compiling process.
build_res2a.log

Ultra96-v2

Hi, I want to run the code on Ultra96-v2. Is it possible? If possible, what should I revise? thank you