xilinx / vitis-tutorials

Vitis In-Depth Tutorials

English | 日本語

AMD Vitis™ In-Depth Tutorials

Visit more Vitis developer videos on Adaptive Computing Developer YouTube Channel

Unlocking a New Design Experience For All Developers

The Vitis software platform is a development environment for developing designs that include FPGA fabric, Arm® processor subsystems, and AI Engines. The Vitis tools work in conjunction with AMD Vivado™ ML Design Suite to provide a higher level of abstraction for design development. Learn how to use Vitis to implement a fully end-to-end application using software-defined flows.

Where to Start

If you are new to the Vitis software platform and want to start with the basics, or just want to get a quick overview of what Vitis can offer, look at the tutorials under Getting Started. From there, explore other tutorials on different topics.

Otherwise, if you are looking for a specific tutorial for the desired device or platform, or are interested in a special application or feature, you can select a tutorial from the topics as listed under the Tutorials.

In this repository, tutorials are divided into different topics by function and application with each topic containing 2 sections.

• Feature Tutorials illustrate specific features or flows of Vitis, Libraries, XRT and platforms, some features may not be required by all designs but are still useful for some use cases.
• Design Tutorials illustrate higher-level concepts or design flows, walk through specific examples or reference designs, and more complex and complete designs or applications.

How to Get Help

• Check the FAQ.
• For questions about the Vitis software platform, visit the Vitis Forum.
• For questions or issues about tutorials, create an Issue.

How to Download the Repository

To get a local copy of the Vitis-Tutorials repository, clone it to your local system by executing the following command:

git clone https://github.com/Xilinx/Vitis-Tutorials.git

The default branch is always consistent with the most recently released version of the Vitis software platform. If you need to run a tutorial on a different version, after you clone the repository, use the git checkout <branch> command to specify a branch that matches the tool version you are using.

Alternatively, you can also download repository contents as a ZIP file. The downloaded ZIP file will contain only the selected branch, and its overall size will be smaller than a cloned repository.

To download a ZIP file of a specific branch, do one of the following:

• From a browser, select the desired branch. Next, click the green Code button and select Download ZIP.

• From a terminal, execute the following command. The following uses the 2023.2 branch as an example.

  wget https://github.com/Xilinx/Vitis-Tutorials/archive/refs/heads/2023.2.zip && unzip 2023.2.zip 
  

Release Notes

Change Log

Tutorials

Getting Started
Start here! Learn the basics of the Vitis programming model by putting together your very first application. No experience necessary!
Vitis Introduction	Vitis HLS Introduction
Vitis Libraries Introduction	Vitis Platform Introduction
Vitis Unified IDE for Embedded Design 🆕

AI Engine Development on AIE-ML 🆕
Learn how to target, develop, and deploy advanced algorithms using Versal AIE-ML architecture in conjunction with PL IP/kernels and software applications running on the embedded processors.
Feature Tutorials		Design Tutorials
A to Z Bare-metal Flow	Using GMIO with AIE-ML	AIE-ML Programming 🆕
Runtime Parameter Reconfiguration	Packet Switching	Versal Custom Thin Platform Extensible System
Versal Integration for HW Emu and HW	AIE Compiler Features 🆕	Prime Factor FFT-1008 on AIE-ML 🆕
AIE-ML Performance Analysis 🆕		AIE-ML LeNet Tutorial 🆕

AI Engine Development on AIE
Learn how to target, develop, and deploy advanced algorithms using a Versal AI Engine array in conjunction with PL IP/kernels and software applications running on the embedded processors.
Feature Tutorials		Design Tutorials
Versal Integration for HW Emu and HW	Using GMIO with AIE	LeNet Tutorial
Runtime Parameter Reconfiguration	Packet Switching	Super Sampling Rate FIR Filters
A to Z Bare-metal Flow	Versal System Design Clocking	Beamforming Design
Using Floating-Point in the AI Engine	DSP Library Tutorial	2D-FFT
Debug Walkthrough Tutorial	AIE DSP Library and Model Composer	FIR Filter
Versal Emulation Waveform Analysis	AXIS External Traffic Generator	N-Body Simulator
AIE Performance and Deadlock Analysis	Implementing an IIR Filter on the AIE	Versal GeMM Implementation
Post-Link Recompile of an AI Engine Application	Python and C++ External Traffic Generators	Polyphase Channelizer
Using RTL IP with AI Engines	AI Engine A-to-Z Flow for Linux	Prime Factor FFT
Using Verilog Traffic Generators in AIE Simulation	Versal Custom Thin Platform Extensible System	Digital Down-conversion Chain
AIE Compiler Features 🆕	Two Tone Filter 🆕	Bilinear Interpolation
Bitonic SIMD Sorting on AI Engine 🆕	FFT and DFT on AI Engine 🆕	64K IFFT Using 2D Architecture 🆕
		Fractional Delay Farrow Filter 🆕

Vitis Embedded Software Development 🆕
Introduce Vitis embedded design flows, learn the Vitis Unified IDE for developing embedded software applications targeted towards AMD embedded processors.
Getting Started	Feature Tutorials
Getting Started in Vitis Unified IDE 🆕	User Managed Mode 🆕	Migrating from classic Vitis IDE to Vitis Unified IDE 🆕
	Vitis Embedded Software Debugging Guide 🆕	Vitis Embedded Scripting Flow 🆕

Vitis HLS 🆕
Vitis High-Level Synthesis (HLS) lets you compile C/C++ code into RTL code. These tutorials offer a broader introduction to the Vitis HLS flows and use cases.
Feature Tutorials		Design Tutorials
Using Code Analyzer from Vitis Unified IDE 🆕	HLS Micro-Optimization Tutorial using Beamformer IP 🆕	Adaptive Beamforming for Radar: Floating-Point QRD+WBS in an FPGA 🆕

Vitis Platform Creation
Learn how to build custom platforms for Vitis to target your own boards built with Xilinx devices, and how to modify and extend existing platforms.
Design Tutorials	Feature Tutorials
Custom Platform Creation on MPSoC	Incorporating Stream Interfaces
Custom Platform Creation on Versal	PetaLinux Building and System Customization
Custom Platform Creation on KV260	Hardware Design Fast Iteration with Vitis Export to Vivado
Versal Custom DFX Platform Creation Tutorial	Versal Extensible Hardware Design Validation

Vitis Developer Contributed Tutorials
Check out tutorials that other developers shared! We welcome your contribution, you may share end-to-end designs, tips and tricks, or designs and examples that can help Xilinx users.
Versal Custom Thin Platform Extensible System	DSP Design on AI Engine with GUI and Makefile Flows
Vitis HLS Optimization Techniques on Embedded Boards

Hardware Acceleration
Learn how to use the Vitis core development kit to build, analyze, and optimize an accelerated algorithm developed in C++, OpenCL, and even Verilog and VHDL.
Feature Tutorials	Design Tutorials
Getting Started with RTL Kernels	Convolution Example
Mixing C and RTL	Bloom Filter Example
Dataflow Debug and Optimization	RTL Systems Integration Example
Using Multiple DDR Banks	Traveling Salesperson Problem
Using Multiple Compute Units	Bottom RTL Kernel Design Flow Example
Controlling Vivado Implementation	Cholesky Algorithm Acceleration
Optimizing for HBM	XRT Host Code Optimization
Host Memory Access	Aurora Kernel on Alveo
Using GT Kernels and Ethernet IPs on Alveo	Single Source Shortest Path Application
P2P Transfer using Native XRT C++ API	Get Moving with Alveo

Other Vitis Tutorial Repositories

Tutorial Repository	Description
Vitis Acceleration Examples	This repository illustrates specific scenarios related to host code and kernel programming through small working examples. They can get you started with Vitis acceleration application coding and optimization.
Machine Learning Tutorials	The repository helps to get you the lay of the land working with machine learning and the Vitis AI toolchain on Xilinx devices. It illustrates specific workflows or stages within Vitis AI and gives examples of common use cases.
Embedded Design Tutorials	Learn how to build and use embedded operating systems and drivers on Xilinx Adaptive SoCs and the MicroBlaze™ soft processor. These tutorials cover open-source operating systems and bare-metal drivers available from Xilinx, compilers, debuggers, and profiling tools for traditional SoC software development.
Vitis Model Composer Tutorials	Learn rapid design exploration using Vitis Model Composer. Vitis Model Composer provides a library of performance-optimized blocks for design and implementation of DSP algorithms on Xilinx devices. The Vitis Model Composer AI Engine, HLS and HDL libraries within the Simulink™ environment, enable the rapid design exploration of an algorithm and accelerate the path to production.

_{Copyright © 2020–2023 Advanced Micro Devices, Inc}

^{Terms and Conditions}

vitis-tutorials's Issues

Specific instructions on setting up SYSROOT and ROOTFS

Hi,

Could you provide more specific instructions on setting up the variables SYSROOT and ROOTFS?
The documentation is pretty vague about how to proceed.

For example, to set up the ZCU102 platform, I have downloaded the ZYNQ common image on this page, and executed sdk.sh as instructed, but what is the correct way to set up SYSROOT and ROOTFS after this step?

Thanks a lot!

"dlopen <path>/dltmp is failed" error message

Hi,

I'm running into an issue trying to run software emulation mode for the zcu102 target. The error message is:

ERROR: dlopen of /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/.run/19717/sw_emu/device0/binary_0/dltmp is failed. Please check undefined symbols in the kernel 

Not quite sure what I've done wrong. Have been following the instructions in this repo with the exception of adapting them for the zcu102 platform. Any ideas?

Thanks,

• J.

In my ~/.bashrc:

source /tools/Xilinx/Vitis/2020.1/settings64.sh
source /opt/xilinx/xrt/setup.sh
export PLATFORM_REPO_PATHS=/opt/xilinx/platforms/

export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu

My design.cfg:

(base) adclab@solo:~/Vitis-Tutorials/docs/Pathway3/reference-files/run$ cat design.cfg 
#platform=xilinx_u200_xdma_201830_2
platform=xilinx_zcu102_base_202010_1
debug=1

[connectivity]
nk=mmult:1:mmult_1

Modified PLATFORM variable in run/Makefile:

 21 TARGET := sw_emu
 22 #PLATFORM := xilinx_u200_xdma_201830_2
 23 PLATFORM := xilinx_zcu102_base_202010_1
 24 HOST_EXE := host
 25 XO := mmult.$(TARGET).$(PLATFORM).xo
 26 XCLBIN := mmult.$(TARGET).$(PLATFORM).xclbin
 27 

Platforms I have installed:

(base) adclab@solo:~/Vitis-Tutorials/docs/Pathway3/reference-files/run$ ls $PLATFORM_REPO_PATHS 
xilinx_zcu102_base_202010_1

(base) adclab@solo:~/Vitis-Tutorials/docs/Pathway3/reference-files/run$ make run TARGET=sw_emu
v++ -t sw_emu --config design.cfg -c -k mmult -I'../src' -o'mmult.sw_emu.xilinx_zcu102_base_202010_1.xo' '../src/mmult.cpp'
Option Map File Used: '/tools/Xilinx/Vitis/2020.1/data/vitis/vpp/optMap.xml'

****** v++ v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
	Reports: /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/reports/mmult.sw_emu.xilinx_zcu102_base_202010_1
	Log files: /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/logs/mmult.sw_emu.xilinx_zcu102_base_202010_1
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:35059
INFO: [v++ 60-1548] Creating build summary session with primary output /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/mmult.sw_emu.xilinx_zcu102_base_202010_1.xo.compile_summary, at Tue Jul 14 13:18:57 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Tue Jul 14 13:18:57 2020
Running Rule Check Server on port:45237
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/reports/mmult.sw_emu.xilinx_zcu102_base_202010_1/v++_compile_mmult.sw_emu.xilinx_zcu102_base_202010_1_guidance.html', at Tue Jul 14 13:18:58 2020
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_zcu102_base_202010_1/xilinx_zcu102_base_202010_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_zcu102_base_202010_1/hw/xilinx_zcu102_base_202010_1.xsa'
INFO: [v++ 60-585] Compiling for software emulation target
INFO: [v++ 60-423]   Target device: xilinx_zcu102_base_202010_1
INFO: [v++ 60-242] Creating kernel: 'mmult'
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-586] Created mmult.sw_emu.xilinx_zcu102_base_202010_1.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/mmult.sw_emu.xilinx_zcu102_base_202010_1.xo.compile_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 16s
INFO: [v++ 60-1653] Closing dispatch client.
v++ -t sw_emu --config design.cfg -l -o'mmult.sw_emu.xilinx_zcu102_base_202010_1.xclbin' mmult.sw_emu.xilinx_zcu102_base_202010_1.xo
Option Map File Used: '/tools/Xilinx/Vitis/2020.1/data/vitis/vpp/optMap.xml'

****** v++ v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
	Reports: /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/reports/link
	Log files: /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/logs/link
INFO: [v++ 60-1657] Initializing dispatch client.
Running Dispatch Server on port:43803
INFO: [v++ 60-1548] Creating build summary session with primary output /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/mmult.sw_emu.xilinx_zcu102_base_202010_1.xclbin.link_summary, at Tue Jul 14 13:19:15 2020
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Tue Jul 14 13:19:15 2020
Running Rule Check Server on port:37647
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/reports/link/v++_link_mmult.sw_emu.xilinx_zcu102_base_202010_1_guidance.html', at Tue Jul 14 13:19:16 2020
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_zcu102_base_202010_1/xilinx_zcu102_base_202010_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_zcu102_base_202010_1/hw/xilinx_zcu102_base_202010_1.xsa'
INFO: [v++ 60-629] Linking for software emulation target
INFO: [v++ 60-423]   Target device: xilinx_zcu102_base_202010_1
INFO: [v++ 60-645] kernel flags are '-g -I /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/src -g'
INFO: [v++ 60-586] Created mmult.sw_emu.xilinx_zcu102_base_202010_1.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
	Guidance: /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/reports/link/v++_link_mmult.sw_emu.xilinx_zcu102_base_202010_1_guidance.html
	Steps Log File: /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/_x/logs/link/link.steps.log

INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/mmult.sw_emu.xilinx_zcu102_base_202010_1.xclbin.link_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 13s
INFO: [v++ 60-1653] Closing dispatch client.
g++ -I/opt/xilinx/xrt/include/ -I/tools/Xilinx/Vivado/2020.1/include/ -Wall -O0 -g -std=c++11 -L/opt/xilinx/xrt/lib/ -lpthread -lrt -lstdc++ -o 'host' '../src/host.cpp' -lOpenCL
emconfigutil --platform xilinx_zcu102_base_202010_1

****** configutil v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [ConfigUtil 60-895]   Target platform: /opt/xilinx/platforms/xilinx_zcu102_base_202010_1/xilinx_zcu102_base_202010_1.xpfm
INFO: [ConfigUtil 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_zcu102_base_202010_1/hw/xilinx_zcu102_base_202010_1.xsa'
emulation configuration file `emconfig.json` is created in current working directory 
XCL_EMULATION_MODE=sw_emu ./host mmult.sw_emu.xilinx_zcu102_base_202010_1.xclbin
Found Platform
Platform Name: Xilinx
INFO: Reading mmult.sw_emu.xilinx_zcu102_base_202010_1.xclbin
Loading: 'mmult.sw_emu.xilinx_zcu102_base_202010_1.xclbin'
ERROR: dlopen of /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/.run/19717/sw_emu/device0/binary_0/dltmp is failed. Please check undefined symbols in the kernel 
XRT build version: 2.6.655
Build hash: 2d6bfe4ce91051d4e5b499d38fc493586dd4859a
Build date: 2020-05-22 12:05:03
Git branch: 2020.1
PID: 19717
UID: 1000
[Tue Jul 14 13:19:21 2020]
HOST: solo
EXE: /home/adclab/Vitis-Tutorials/docs/Pathway3/reference-files/run/host
[XRT] ERROR: Failed to load xclbin.
../src/host.cpp:200 Error calling cl::Program program(context, devices, bins, NULL, &err), error code is: -44
Makefile:59: recipe for target 'run' failed
make: *** [run] Error 1

Missing step in packaging IP documentation

In the Hardware_Accelerators/Feature_Tutorials/01-rtl_kernel_workflow/package_ip.md documentation, I have reached the "Check Integrity, Assign Properties, and Package IP" step where step 2 tells me to run the following commands in the Tcl console to "set these properties" with no reference to what "these properties" might mean.

set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} $core
set_property sdx_kernel true $core
set_property sdx_kernel_type rtl $core

Also, the above lines result in the error can't read "core": no such variable.

Is there something I need to set before running these lines? And also which file should I run check_integrity on?

Can vai_q_pytorch support torch.autograd.Function's derived class called by forward function?

I am doing a new deep learning algorithm research with my own torch.aotograd.Function derived class, but I met 'parsing failed(unsupported)' when quantizing with vitis-ai-pytorch. Does vitis-ai-pytorch support users' own autograd class, or does vitis-ai-pytorch support another class except the model class?

I got the following info:

(vitis-ai-pytorch) Vitis-AI /workspace/workplace/BP > python -u quantize.py --quant_mode calib 2>&1 | tee quant_calib.log
No CUDA runtime is found, using CUDA_HOME='/usr/local/cuda'

[NNDCT_NOTE]: Loading NNDCT kernels...

-----------------------------------------
PyTorch version : 1.4.0
3.6.12 |Anaconda, Inc.| (default, Sep 8 2020, 23:10:56)
[GCC 7.3.0]
-----------------------------------------
Command line options:
--dset_dir : dataset
--float_model : float_model
--quant_mode : calib
--batchsize : 100
--quant_model : quant_model
-----------------------------------------
No CUDA devices available..selecting CPU

[NNDCT_WARN]: CUDA is not available, change device to CPU

[NNDCT_NOTE]: Quantization calibration process start up...

[NNDCT_NOTE]: =>Quant Module is in 'cpu'.

[NNDCT_NOTE]: =>Parsing SCNN...
aten_op 'ActFun' parse failed(unsupported)

And part of my code:

class ActFun(torch.autograd.Function):



    @staticmethod

    def forward(ctx, input):

        ctx.save_for_backward(input)

        return input.gt(thresh).float()



    @staticmethod

    def backward(ctx, grad_output):

        input, = ctx.saved_tensors

        grad_input = grad_output.clone()

        temp = abs(input - thresh) < lens

        return grad_input * temp.float()



act_fun = ActFun.apply

# membrane potential update

def mem_update(ops, x, mem, spike):

    mem = mem * decay * (1. - spike) + ops(x)

    spike = act_fun(mem) # act_fun : approximation firing function

    return mem, spike

I call mem_update in my forward function.

My quantize.py is almost the same as quantize.py (github: Vitis-Tutorials/Machine_Learning/Design_Tutorials/09-mnist_pyt_master/files/quantize.py)

Thank you so much.

Custom platorm (PCIe based cards)

Hi,

Is there any example / tutorial how to make a custom platform for a PCIe based card, for example KC705?

.dtsi file for ultra96 v2

Hi,

I have a question regarding the Vitis_Platform_Creation:

https://github.com/Xilinx/Vitis-Tutorials/blob/master/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104/step2.md

What should I fill for the .dtsi file of ultra96 v2.

[XRT] WARNING: Profiling may contain incomplete information.

Hi, I am running the example in the tutorial https://github.com/Xilinx/Vitis-Tutorials/tree/master/Getting_Started/Vitis with u200.

I got this message after run app.exe

 $ ./app.exe
INFO: Found Xilinx Platform
INFO: Loading 'vadd.xclbin'
ERROR : [SW-EM 10] Please make sure that the XILINX_VITIS environment variable is set correctly
XRT build version: 2.7.766
Build hash: 19bc791a7d9b54ecc23644649c3ea2c2ea31821c
Build date: 2020-08-17 16:52:05
Git branch: 2020.1_PU1
PID: 2614
UID: 1000
[Tue Dec 1 14:39:05 2020 GMT]
HOST: iu-virtual-machine
EXE: /home/iu/work/workspace/example/u200/sw_emu/app.exe
[XRT] WARNING: Profiling may contain incomplete information. Please ensure all OpenCL objects are released by your host code (e.g., clReleaseProgram()).

The Vitis environment variables have been set and I can run v++ anywhere, so I don't think the problem is the env.

And how about the XRT warning? Should I add clReleaseProgram() in the host.cpp?

Thanks a lot.

HW_EMU (hardware emulation) errors in the Cholesky example (temporally solved)

In the Cholesky example here (Vitis-Tutorials/Hardware_Accelerators/Introduction/03-Algorithm_Acceleration/docs/module1_baseline), running make run TARGET=hw_emu fails.
Meanwhile, running make run TARGET=sw_emu succeeds.

Specifically, the error information is:

[XRT] WARNING: Argument '1' of kernel 'cholesky_kernel' is allocated in memory bank 'bank0'; compute unit 'cholesky_kernel_1' cannot be used with this argument and is ignored.
[XRT] ERROR: kernel 'cholesky_kernel' has no compute units to support required argument connectivity.
ERROR: clSetKernelArg() for kernel "cholesky_kernel", argument index 1. 

The error is very likely coming from this line, and it seems to be related to memory allocation/transfer and/or kernel argument setup, potentially function clSetKernelArg.

Could anyone help? Any suggestion/hint would be appreciated!

Environment:
OS: Ubuntu 18.04; Device: xilinx_u200_xdma_201830_2; XRT build version: 2.8.0.

A screenshot of the error information is shown below.

ERROR: [v++ 60-1576] Input Object file validation failed: zip_exception: Failed to open zip archive for reading

I am trying to compile the vadd example provided with Vitis 2020.2. As I want to prepare my custom Makefile I have started with super simple stuff.
I first run

v++ --platform xilinx_u50_gen3x16_xdma_201920_3  -c src/example/kernel/krnl_vadd.cpp -o build/krnl_vadd.xo

It seems to work correctly.
Then, I run

v++ -l --platform xilinx_u50_gen3x16_xdma_201920_3  build/krnl_vadd.xo -o bin/ExampleKrnl.xclbin

However, during the built I get following error:

ERROR: [v++ 60-1576] Input Object file validation failed: zip_exception: Failed to open zip archive for reading build/krnl_vadd.xo

I have tried to google the problem, but without success.
Theoretically I use OS which is supported by Xilinx, Ubuntu 20.04.

Does anyone know what might be wrong?

YOLOv4 KeyError: 'up_sampling2d/mul'

Hello,
I've been trying to follow the YOLOv4 tutorial for Vitis AI 1.3, and I am stuck with the compilation stage where I get the following error:

**************************************************
* VITIS_AI Compilation - Xilinx Inc.
**************************************************
[INFO] Namespace(inputs_shape=['1,416,416,3'], layout='NHWC', model_files=['./quantize/quantize_eval_model.pb'], model_type='tensorflow', out_filename='./compiled/yolov4_org.xmodel', proto=None)
in_shapes: [[1, 416, 416, 3]]
[INFO] tensorflow model: quantize/quantize_eval_model.pb
[INFO] parse raw model     :100%|███████████████████████████████████████████████████████████████████████████████████████████████████████████| 526/526 [00:00<00:00, 25868.00it/s]             
Traceback (most recent call last):
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/bin/xnnc-run", line 33, in <module>
    sys.exit(load_entry_point('xnnc==1.3.0', 'console_scripts', 'xnnc-run')())
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/__main__.py", line 194, in main
    normal_run(args)
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/__main__.py", line 178, in normal_run
    in_shapes=in_shapes if len(in_shapes) > 0 else None,
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/xconverter.py", line 131, in run
    xmodel = CORE.make_xmodel(model_files, model_type, _layout, in_shapes)
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/core.py", line 104, in make_xmodel
    model_files, layout, in_shapes=in_shapes, model_type=model_t
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/translator/tensorflow_translator.py", line 97, in to_xmodel
    model_name, raw_nodes, layout, in_shapes, model_fmt, model_type
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/translator/tensorflow_translator.py", line 161, in create_xmodel
    xmodel = cls.__create_xmodel_from_tf1(name, layers, layout, in_shapes)
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/translator/tensorflow_translator.py", line 284, in __create_xmodel_from_tf1
    cls.__specialcase_replace_elemadd_with_biasadd(xmodel)
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/translator/tensorflow_translator.py", line 3406, in __specialcase_replace_elemadd_with_biasadd
    xmodel.topsort()
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/ir/xmodel.py", line 190, in topsort
    indegree_xnode[cname] -= 1
KeyError: 'up_sampling2d/mul'

When I run with Vitis AI 1.2, it compiles fine but outputs the older elf format, not xmodel. Is there something I am missing from my compile script? Also, I converted the Darknet weights to PB with the YOLOv3 model-set project that was recommended in the tutorial, and both the normal and quantized weights run fine in Vitis.

TARGET=ZCU104
NET_NAME=yolov4

ARCH=/opt/vitis_ai/compiler/arch/DPUCZDX8G/${TARGET}/arch.json

vai_c_tensorflow --frozen_pb ./quantize/quantize_eval_model.pb \
		 --arch ${ARCH} \
		 --output_dir ./compiled \
		 --net_name ${NET_NAME} \
		 --options "{'mode':'normal', 'save_kernel':'', 'input_shape':'1,416,416,3'}"

线程问题

您好：
请问一下。为什么在使用./test_video_yolov3 dpu_yolov4_voc 0 -t4时，t无论是1还是4，检测的FPS都是一样的？

Unable to reprogram FPGA and run NEW kernels in combination with XRT, affects both non-DFX and DFX base platforms

Context

This ticket's part of a debugging effort and connected to past issues including #69 #70 #71 and #72.

While developing kernels it's common to test (also in hw target) incremental variants of it. So far, unfortunately, I haven't been able to do so. Only the first kernel produced (the first time the sd card is introduced is the hardware) remains. I haven't been able to successfully change this. The current issues has been validated in the following hardware and base platform combinations:

Hardware	Base platform
ZCU102	xilinx_zcu102_base_202020_1
ZCU102	xilinx_zcu102_base_dfx_202020_1
ZCU104	xilinx_zcu104_base_202020_1

A simple way to reproduce this is to build and test variants (silly ones, simple modifications of the kernel) of https://github.com/Xilinx/Vitis-Tutorials/tree/master/Getting_Started/Vitis. An exemplary flow to reproduce this issue is as follows:

1. Follow https://github.com/Xilinx/Vitis-Tutorials/blob/master/Getting_Started/Vitis/Part4.md and build the sd_card.img
2. Flash raw image into SD card and boot
3. Run app.exe obtaining results coherent to the vadd.xclbin kernel (whatever they are)
4. Modify vadd.cpp (source code) introduce a small (or big, up to you) change
5. Rebuild kernel with Vitis v++ compiler
6. Scp kernel to hardware as vadd.xclbin.new for DFX platforms (or just build the whole image complete again with v++ -p for non-DFX platforms)
7. Run app.exe vadd.xclbin.new

The expected observation is that result remains fixed to 3. and not related to the changes introduced in 4., 5. and 6.. A past issue in XRT identified a similar behavior Xilinx/XRT#2747.

Results so far

NOTE: I'm using Vitis suite 2020.2 on top of Ubuntu 20.04.
NOTE 2: Ignore paths, they're specific to my development machines.

xilinx_zcu102_base_202020_1

Regardless of what I do the result's always the same which corresponds with the first kernel I flashed which modified https://github.com/Xilinx/Vitis-Tutorials/blob/master/Getting_Started/Vitis/example/src/vadd.cpp#L15 to:

$$out = in1 + 2 * in2$$

cd /home/xilinx/Vitis-Tutorials/Getting_Started/Vitis/example/zcu102/hw; rm -r package/ _x/ vadd.x* app.exe a.xclbin v++*

# configure env.
source /tools/Xilinx/Vitis/2020.2/settings64.sh
export PLATFORM_REPO_PATHS=/home/xilinx/xilinx_zcu102_base_202020_1
export ROOTFS=/home/xilinx/rootfs
source /home/xilinx/rootfs/sdk/environment-setup-aarch64-xilinx-linux

# build
${CXX} -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++
v++ -c -t hw --config ../../src/zcu102.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo
v++ -l -t hw --config ../../src/zcu102.cfg ./vadd.xo -o vadd.xclbin
v++ -p -t hw --config ../../src/zcu102.cfg ./vadd.xclbin --package.out_dir package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file xrt.ini --package.sd_file app.exe --package.sd_file vadd.xclbin --package.sd_file run_app.sh

# test acceleration
cd /media/sd-mmcblk0p1
export XILINX_XRT=/usr
./app.exe vadd.xclbin

root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# ./app.exe vadd.xclbin
[  265.853107] [drm] Pid 1221 opened device
[  265.857065] [drm] Pid 1221 closed device
INFO: Found Xilinx Platform
[  265.863503] [drm] Pid 1221 opened device
[  265.869667] [drm] Pid 1221 closed device
[  265.873637] [drm] Pid 1221 opened device
INFO: Loading 'vadd.xclbin'
[  265.962660] [drm] zocl_xclbin_read_axlf The XCLBIN already loaded
[  265.962676] [drm] zocl_xclbin_read_axlf c82ababc-a138-4cb2-bfd8-595f8a4cd9b3 ret: 0
[  265.971245] [drm] bitstream c82ababc-a138-4cb2-bfd8-595f8a4cd9b3 locked, ref=1
[  265.978917] [drm] Reconfiguration not supported
[  265.990677] [drm] bitstream c82ababc-a138-4cb2-bfd8-595f8a4cd9b3 unlocked, ref=0
[  265.991808] [drm] bitstream c82ababc-a138-4cb2-bfd8-595f8a4cd9b3 locked, ref=1
[  266.005109] [drm] User buffer is not physical contiguous
Error: Result mismatch
i = 0 CPU result = 2349 Device result = 4281
TEST FAILED
... (continues)

xilinx_zcu102_base_dfx_202020_1

cd /home/xilinx/Vitis-Tutorials/Getting_Started/Vitis/example/zcu102/hw; rm -r package/ _x/ vadd.x* app.exe a.xclbin v++*

# configure env.
source /tools/Xilinx/Vitis/2020.2/settings64.sh
export PLATFORM_REPO_PATHS=/home/xilinx/xilinx_zcu102_base_dfx_202020_1
export ROOTFS=/home/xilinx/rootfs
source /home/xilinx/rootfs/sdk/environment-setup-aarch64-xilinx-linux

# build
${CXX} -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++
v++ -c -t hw --config ../../src/zcu102_dfx.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo
v++ -l -t hw --config ../../src/zcu102_dfx.cfg ./vadd.xo -o vadd.xclbin
v++ -p -t hw --config ../../src/zcu102_dfx.cfg ./vadd.xclbin --package.out_dir package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file xrt.ini --package.sd_file app.exe --package.sd_file vadd.xclbin --package.sd_file run_app.sh

# test acceleration
cd /media/sd-mmcblk0p1
export XILINX_XRT=/usr
./app.exe vadd.xclbin

root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# ./app.exe vadd.xclbin
[  265.853107] [drm] Pid 1221 opened device
[  265.857065] [drm] Pid 1221 closed device
INFO: Found Xilinx Platform
[  265.863503] [drm] Pid 1221 opened device
[  265.869667] [drm] Pid 1221 closed device
[  265.873637] [drm] Pid 1221 opened device
INFO: Loading 'vadd.xclbin'
[  265.962660] [drm] zocl_xclbin_read_axlf The XCLBIN already loaded
[  265.962676] [drm] zocl_xclbin_read_axlf c82ababc-a138-4cb2-bfd8-595f8a4cd9b3 ret: 0
[  265.971245] [drm] bitstream c82ababc-a138-4cb2-bfd8-595f8a4cd9b3 locked, ref=1
[  265.978917] [drm] Reconfiguration not supported
[  265.990677] [drm] bitstream c82ababc-a138-4cb2-bfd8-595f8a4cd9b3 unlocked, ref=0
[  265.991808] [drm] bitstream c82ababc-a138-4cb2-bfd8-595f8a4cd9b3 locked, ref=1
[  266.005109] [drm] User buffer is not physical contiguous
Error: Result mismatch
i = 0 CPU result = 2349 Device result = 4281
TEST FAILED

(gets stucked in here)

xilinx_zcu104_base_202020_1

cd /home/xilinx/Vitis-Tutorials/Getting_Started/Vitis/example/zcu104/hw
# configure env.
source /tools/Xilinx/Vitis/2020.2/settings64.sh
export PLATFORM_REPO_PATHS=/home/xilinx/xilinx_zcu104_base_202020_1
# export ROOTFS=/home/xilinx/rootfs
export ROOTFS=/home/xilinx/petalinux-xilinx-zcu104-2020.2/images/linux
source /home/xilinx/rootfs/sdk/environment-setup-aarch64-xilinx-linux

# build
${CXX} -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++
v++ -c -t hw --config ../../src/zcu104.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo
v++ -l -t hw --config ../../src/zcu104.cfg ./vadd.xo -o vadd.xclbin
v++ -p -t hw --config ../../src/zcu104.cfg ./vadd.xclbin --package.out_dir package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file xrt.ini --package.sd_file app.exe --package.sd_file vadd.xclbin --package.sd_file run_app.sh

# run
...
TEST PASSED

I haven't been able to get tests to fail after this. Regardless of the modifications in the kernels.

Additional tests performed

Reinstalled Vitis suite and PetaLinux completely in a newly formatted machine with Ubuntu 20.04. Same result.

Temporary fix

A user proposed a temporary fix flashing manually the FPGA which I have not been able to reproduce Xilinx/XRT#2747 (comment). Here're my results when attempting this:

xilinx_zcu104_base_202020_1

# in the workstation
xclbinutil --dump-section BITSTREAM:RAW:vadd.bit -i vadd.xclbin
# then scp-it to embedded

# in the embedded platform
cd /media/sd-mmcblk0p1
export XILINX_XRT=/usr
fpgautil -b ./vadd.bit
root@xilinx-zcu104-2020_2:/media/sd-mmcblk0p1# ./app.exe
[  158.257308] [drm] Pid 1028 opened device
[  158.261267] [drm] Pid 1028 closed device
INFO: Found Xilinx Platform
[  158.267677] [drm] Pid 1028 opened device
[  158.273834] [drm] Pid 1028 closed device
[  158.277794] [drm] Pid 1028 opened device
INFO: Loading 'vadd.xclbin'
[  158.430057] [drm] zocl_xclbin_read_axlf The XCLBIN already loaded
[  158.430073] [drm] zocl_xclbin_read_axlf 030235fc-c6ab-4195-83b3-00e2e0860b11 ret: 0
[  158.438503] [drm] bitstream 030235fc-c6ab-4195-83b3-00e2e0860b11 locked, ref=1
[  158.446209] [drm] Reconfiguration not supported
[  158.457973] [drm] bitstream 030235fc-c6ab-4195-83b3-00e2e0860b11 unlocked, ref=0

(gets stucked in here)

Further debugging this issue led to a kernel panic:

root@xilinx-zcu104-2020_2:~# cd /media/sd-mmcblk0p1
root@xilinx-zcu104-2020_2:/media/sd-mmcblk0p1# export XILINX_XRT=/usr
root@xilinx-zcu104-2020_2:/media/sd-mmcblk0p1# fpgautil -b ./vadd.bit
[   42.264337] fpga_manager fpga0: writing vadd.bit to Xilinx ZynqMP FPGA Manager
Time taken to load BIN is 9302.000000 Milli Seconds
BIN FILE loaded through FPGA manager successfully
root@xilinx-zcu104-2020_2:/media/sd-mmcblk0p1#
root@xilinx-zcu104-2020_2:/media/sd-mmcblk0p1#
root@xilinx-zcu104-2020_2:/media/sd-mmcblk0p1# ls
BOOT.BIN  boot.scr	     profile_summary.csv  timeline_trace.csv  xrt.ini
Image	  init.sh	     run_app.sh		  vadd.bit
app.exe   platform_desc.txt  system.dtb		  vadd.xclbin
root@xilinx-zcu104-2020_2:/media/sd-mmcblk0p1# gdb ./app.exe
GNU gdb (GDB) 8.3.1
Copyright (C) 2019 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "aarch64-xilinx-linux".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
    <http://www.gnu.org/software/gdb/documentation/>.

For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from ./app.exe...
(gdb) r
Starting program: /media/sd-mmcblk0p1/app.exe
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/libthread_db.so.1".
[   81.754011] Unable to handle kernel NULL pointer dereference at virtual address 00000000000007f3
[   81.762787] Mem abort info:
[   81.765563]   ESR = 0x96000004
[   81.768601]   EC = 0x25: DABT (current EL), IL = 32 bits
[   81.773895]   SET = 0, FnV = 0
[   81.776933]   EA = 0, S1PTW = 0
[   81.780057] Data abort info:
[   81.782922]   ISV = 0, ISS = 0x00000004
[   81.786741]   CM = 0, WnR = 0
[   81.789695] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000877e81000
[   81.796116] [00000000000007f3] pgd=0000000000000000
[   81.800978] Internal error: Oops: 96000004 [#1] SMP
[   81.805838] Modules linked in: dmaproxy(O) mali(O) zocl(O)
[   81.811319] CPU: 0 PID: 977 Comm: gdb Tainted: G           O      5.4.0-xilinx-v2020.2 #1
[   81.819483] Hardware name: ZynqMP ZCU104 RevC (DT)
[   81.824258] pstate: a0000085 (NzCv daIf -PAN -UAO)
[   81.829039] pc : xilinx_dpdma_chan_err_task+0xe0/0x1b8
[   81.834162] lr : xilinx_dpdma_chan_err_task+0x1c/0x1b8
[   81.839281] sp : ffff800010003e40
[   81.842580] x29: ffff800010003e40 x28: 0000000000000000
[   81.847875] x27: 0000000000000038 x26: 0000000000000060
[   81.853169] x25: 0000000000000040 x24: 00000000000000e0
[   81.858464] x23: ffff00087a37f140 x22: ffff8000110c1b00
[   81.863759] x21: 0000000000000000 x20: ffff000879678c80
[   81.869054] x19: ffff0008796eae80 x18: 0000000000000000
[   81.874348] x17: 0000000000000000 x16: 0000000000000000
[   81.879643] x15: 0000000000000000 x14: 5f3874534e497373
[   81.884938] x13: 656363615f4d5f39 x12: 617461645f796e41
[   81.890233] x11: 5f3974534b4e5a5f x10: 0000000000000040
[   81.895528] x9 : ffff8000110f5368 x8 : ffff8000110f5360
[   81.900822] x7 : ffff00087f777858 x6 : ffff800010003dc0
[   81.906117] x5 : ffff80086e6bf000 x4 : 0000000000000000
[   81.911412] x3 : 0000000000000001 x2 : ffff00087682dcc8
[   81.916707] x1 : ffff00087682dc80 x0 : 03000000000006f3
[   81.922002] Call trace:
[   81.924435]  xilinx_dpdma_chan_err_task+0xe0/0x1b8
[   81.929210]  tasklet_action_common.isra.0+0xcc/0x178
[   81.934164]  tasklet_action+0x24/0x30
[   81.937811]  __do_softirq+0x118/0x22c
[   81.941456]  irq_exit+0x98/0xc0
[   81.944581]  __handle_domain_irq+0x64/0xb8
[   81.948659]  gic_handle_irq+0x5c/0xb8
[   81.952305]  el1_irq+0xb8/0x140
[   81.955433]  __arch_copy_to_user+0x1a0/0x218
[   81.959694]  copy_page_to_iter+0xe8/0x338
[   81.963687]  generic_file_read_iter+0x384/0xb28
[   81.968210]  ext4_file_read_iter+0x38/0x50
[   81.972297]  new_sync_read+0xe4/0x170
[   81.975941]  __vfs_read+0x2c/0x40
[   81.979239]  vfs_read+0xb8/0x190
[   81.982451]  ksys_read+0x68/0xf0
[   81.985663]  __arm64_sys_read+0x18/0x20
[   81.989484]  el0_svc_common.constprop.0+0x68/0x160
[   81.994265]  el0_svc_handler+0x6c/0x88
[   81.997997]  el0_svc+0x8/0xc
[   82.000865] Code: f8448c40 eb00005f d1040000 540000a0 (f9408000)
[   82.006952] ---[ end trace 1b932a3dbbd74e07 ]---
[   82.011555] Kernel panic - not syncing: Fatal exception in interrupt
[   82.017891] SMP: stopping secondary CPUs
[   82.021799] Kernel Offset: disabled
[   82.025269] CPU features: 0x0002,20002004
[   82.029260] Memory Limit: none
[   82.032302] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]---

xilinx_zcu102_base_dfx_202020_1

# in the workstation
xclbinutil --dump-section BITSTREAM:RAW:vadd.bit -i vadd.xclbin
# then scp-it to embedded

# in the embedded platform
cd /media/sd-mmcblk0p1
export XILINX_XRT=/usr
fpgautil -b ./vadd.bit

root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# fpgautil -b ./vadd.bit
[  430.136806] fpga_manager fpga0: writing vadd.bit to Xilinx ZynqMP FPGA Manager
[  445.466900] mmc0: Timeout waiting for hardware interrupt.
[  445.472292] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
[  445.478714] mmc0: sdhci: Sys addr:  0x00000000 | Version:  0x00001002
[  445.485137] mmc0: sdhci: Blk size:  0x00007200 | Blk cnt:  0x00000000
[  445.491560] mmc0: sdhci: Argument:  0x0042c800 | Trn mode: 0x00000027
[  445.497983] mmc0: sdhci: Present:   0x01ff0000 | Host ctl: 0x0000001f
[  445.504406] mmc0: sdhci: Power:     0x0000000f | Blk gap:  0x00000080
[  445.510830] mmc0: sdhci: Wake-up:   0x00000000 | Clock:    0x00000207
[  445.517253] mmc0: sdhci: Timeout:   0x00000009 | Int stat: 0x00000002
[  445.523676] mmc0: sdhci: Int enab:  0x03ff008b | Sig enab: 0x03ff008b
[  445.530099] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000001
[  445.536522] mmc0: sdhci: Caps:      0x35ecc881 | Caps_1:   0x00002007
[  445.542945] mmc0: sdhci: Cmd:       0x0000193a | Max curr: 0x00000000
[  445.549369] mmc0: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0x003b377f
[  445.555792] mmc0: sdhci: Resp[2]:   0x325b5900 | Resp[3]:  0x00000c00
[  445.562214] mmc0: sdhci: Host ctl2: 0x00000001
[  445.566643] mmc0: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x000000087926d2c0
[  445.573759] mmc0: sdhci: ============================================
[  456.306892] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[  456.312799] rcu: 	0-...0: (1 GPs behind) idle=926/0/0x1 softirq=4120/4121 fqs=2596
[  456.320444] rcu: 	1-...0: (1 GPs behind) idle=e82/1/0x4000000000000000 softirq=2437/2438 fqs=2596
[  456.329391] 	(detected by 3, t=5257 jiffies, g=8457, q=24)
[  456.334858] Task dump for CPU 0:
[  456.338071] swapper/0       R  running task        0     0      0 0x0000000a
[  456.345109] Call trace:
[  456.347548]  __switch_to+0x1c4/0x288
[  456.351108]  0xffff8000110d98a8
[  456.354232] Task dump for CPU 1:
[  456.357443] sh              R  running task        0  1257   1253 0x00000022
[  456.364482] Call trace:
[  456.366915]  __switch_to+0x1c4/0x288
[  456.370472]  0xfffffe0021cd95c0

(board hangs in here)

Questions

• I was surprised that this (by "this" I mean the development flows explained above in Context) couldn't work in non-DFX platforms. Is this expected to work in non-DFX platforms? If not, what's the proposal for reprogramming the FPGA with XRT flows? addressed in #74 (comment)
• I was very surprised that I couldn't get this flow working even with DFX base platform. Can you confirm this should work with DFX platforms?
• Since none of the above worked and the proposed fix in a past issue only led to more issues, how can I manually reprogram FPGAs for using them with XRT? addressed in #74 (comment)

I'm currently blocked with this (and have been blocked by it for more than a week already) so It'd be great if someone could help with it or suggest and alternative route. Anything for ZCU102 or ZCU104 would do.
Thanks!

$(CXX) doesn't make sense for cross-compilation in Tutorials

Cross-compilation of binaries at https://github.com/Xilinx/Vitis-Tutorials/blob/master/Getting_Started/Vitis/Part4.md is described as:

cd <Path to the cloned repo>/Getting_Started/Vitis/example/zcu102/sw_emu

$(CXX) -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++

I don't really know what you mean with $(CXX). Maybe it's a syntax I don't know (nor I can make it work). Do you mean $(echo $CXX).

Typos in my-first-program/profile_debug.md

Step 6 says, "Notice that the highlighted calls clProgramWithBinary, clEnqueueMigrateMemObjects and clEnqueueTask are consuming most of the application time."

No calls are highlighted in the preceding figure. Either the figure should be edited to highlight content, or this sentence should be changed to drop mention to highlighting.

Also, clProgramWithBinary is called clCreateProgramWithBinary in the figure.

Also, the text does not really reflect what's shown in the figure. Perhaps it should say, clCreateProgramWithBinary and clFinish are consuming most of the application time.

Compile yolov4 with custom data set output no DPU graph

Hello Xilinx's member

I tried to follow tutorial "Vitis-Tutorials/Machine_Learning/Design_Tutorials/07-yolov4-tutorial/" to execute Yolov4 to Ultra96v2.
I used custom dataset. I found that there is no graph in DPU.

[UNILOG][INFO] The compiler log will be dumped at "/tmp/vitis-ai-user/log/xcompiler-20210319-091311-818"
[UNILOG][INFO] Target architecture: DPUCZDX8G_ISA0_B2304_MAX_BG2
[UNILOG][INFO] Compile mode: dpu
[UNILOG][INFO] Debug mode: function
[UNILOG][INFO] Target architecture: DPUCZDX8G_ISA0_B2304_MAX_BG2
[UNILOG][INFO] Graph name: deploy, with op num: 693
[UNILOG][INFO] Begin to compile...
[UNILOG][INFO] Total device subgraph number 2, DPU subgraph number 0
[UNILOG][INFO] Compile done

Could you please tell me the reason?
Thank you very much!

[HLS] Disable Automatic Loop Optimizations

As mentioned in this tutorial here, 'simple loops and inner loops (for nested loops) are automatically pipelined by the tool'.

I hope to know is there is any reference to the documentation about the pipelining optimizations automatically applied?
Is it possible to disable such optimizations, e.g., maybe by changing some compiler configurations?

Thanks!

question about val/train images for yolov4 tutorial

For the tensorflow workflow there are scripts to generate val/train images. From the scripts it looks as though the images and labels should go in the same location. Is this correct?

https://github.com/Xilinx/Vitis-Tutorials/blob/master/Machine_Learning/Design_Tutorials/07-yolov4-tutorial/scripts/gen_yolo_val_labels.sh

If it is, then I'm not sure why this section of the annotation creation script is removing that directory

https://github.com/Xilinx/Vitis-Tutorials/blob/master/Machine_Learning/Design_Tutorials/07-yolov4-tutorial/scripts/gen_coco_annotations.py#L72

Could you clarify?

Should I use different directories and then move the txt files over after they are created?

failed software emulation: ../../src/host.cpp:33:10: fatal error: vector: No such file or directory

Hi. I need some help with the software emulation. I think I follow the instructions clearly for each step and I export the all the path/ However when I run the software emulation "aarch64-linux-gnu-g++ -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I${SYSROOT}/usr/include/xrt -L${SYSROOT}/usr/lib -lOpenCL -lpthread -lrt -lstdc++ --sysroot=${SYSROOT}", it keeps telling me:

../../src/host.cpp:33:10: fatal error: vector: No such file or directory
33 | #include
| ^~~~~~~~
compilation terminated.

I am not sure why this happen, vector should be included in g++ library. Am I missing something here?

Help/intuition debugging vadd example (Getting_Started/Vitis), zocl-drm amba:zyxclmm_drm: swiotlb buffer is full

Greetings,

First let me credit authors and maintainers for this repository. From the top of the list cheers for @xlinx-dachang, @rwarmstr and @f-rivo among others. Well done. I found the material very useful and the quality rather high. I'm excited about these tutorials and I believe many share the same vision. Maybe I'll get a chance to contribute in the future myself with some additional tutorials :).

I'm launching here a request for help/pointers debugging an issue that probably some other may have encountered (or will). The accelerated kernels I'm developing are slowly building on top of the examples provided. I found vadd one incredibly illustrative so I'll use this one to motivate the problem:

The PS-side of the code uses a DATA_SIZE pre-processor definition to determine the size of the vectors to be used. The example uses a default size of 4096. If (like me) you happen to be dealing with data-structures a bit more dense than this, you'd typically try other values:

//#define DATA_SIZE 4096  // 2**12
#define DATA_SIZE 65536  // 2**16
//#define DATA_SIZE 262144  // 2**18

While testing with the hw_emu build target (see build targets), 4096 and 65536 produce the expected results but when testing with 262144, the following occurs:

devmachine# ./app.exe.262144
INFO: Add accelerated vector example
INFO: Found Xilinx Platform
[  236.229053] [drm] Pid 828 opened device
INFO: Loading 'vadd.xclbin'
[  236.692526] [drm] zocl_xclbin_read_axlf The XCLBIN already loaded
[  236.692575] [drm] zocl_xclbin_read_axlf 66bc6e53-9c1d-4127-b026-d1f6829206f7 ret: 0
[  236.705650] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 locked, ref=1
[  236.706336] [drm] Reconfiguration not supported
[  236.708989] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 unlocked, ref=0
[  236.725520] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 locked, ref=1
[  236.753934] zocl-drm amba:zyxclmm_drm: swiotlb buffer is full (sz: 1048576 bytes), total 32768 (slots), used 408 (slots)
[  236.756095] zocl-drm amba:zyxclmm_drm: overflow 0x0000000873069000+1048576 of DMA mask ffffffff bus mask 0
[  236.756350] ------------[ cut here ]------------
[  236.756687] WARNING: CPU: 3 PID: 828 at kernel/dma/direct.c:35 report_addr+0x38/0xa0
[  236.757377] Modules linked in: zocl(O)
[  236.757842] CPU: 3 PID: 828 Comm: app.exe.262144 Tainted: G        W  O      5.4.0-xilinx-v2020.2 #1
[  236.758102] Hardware name: ZynqMP ZCU102 Rev1.0 (DT)
[  236.758233] pstate: 80000005 (Nzcv daif -PAN -UAO)
[  236.758359] pc : report_addr+0x38/0xa0
[  236.758439] lr : report_addr+0x98/0xa0
[  236.758535] sp : ffff800011b0bb10
[  236.758619] x29: ffff800011b0bb10 x28: ffff800011b0bcf8
[  236.758914] x27: 0000000000000018 x26: ffff00087ab0fc00
[  236.759088] x25: ffff0008793d0780 x24: 0000000000000000
[  236.759227] x23: 0000000000000000 x22: ffff00087ab4dc10
[  236.759363] x21: 0000000000100000 x20: ffff00087a31b140
[  236.759443] x19: ffff00087ab4dc10 x18: 0000000000000010
[  236.759524] x17: 0000000000000041 x16: 0000000000000000
[  236.759662] x15: ffff00087a31b568 x14: 616d20414d442066
[  236.759818] x13: 6f20363735383430 x12: 312b303030393630
[  236.760174] x11: 3337383030303030 x10: 3030783020776f6c
[  236.760318] x9 : ffff800011193000 x8 : 0000000000000220
[  236.760464] x7 : 0000000000000006 x6 : 0000000000000001
[  236.760610] x5 : 0000000000000000 x4 : 0000000000000001
[  236.760778] x3 : 0000000000000006 x2 : 9ca27b1d401e1900
[  236.760946] x1 : 9ca27b1d401e1900 x0 : 0000000000000000
[  236.761277] Call trace:
[  236.761342]  report_addr+0x38/0xa0
[  236.762441]  dma_direct_map_page+0x110/0x130
[  236.762571]  dma_direct_map_sg+0x78/0xe0
[  236.763016]  zocl_userptr_bo_ioctl+0x16c/0x2c8 [zocl]
[  236.763185]  drm_ioctl_kernel+0xb8/0x108
[  236.763408]  drm_ioctl+0x200/0x410
[  236.763495]  do_vfs_ioctl+0x878/0xa20
[  236.763625]  ksys_ioctl+0x44/0x90
[  236.763738]  __arm64_sys_ioctl+0x1c/0x28
[  236.763849]  el0_svc_common.constprop.0+0x68/0x160
[  236.763976]  el0_svc_handler+0x6c/0x88
[  236.764049]  el0_svc+0x8/0xc
[  236.764111] ---[ end trace e731bc0ce1c1afd2 ]---
[  236.764900] [drm:zocl_userptr_bo_ioctl [zocl]] *ERROR* Map SG list failed
[  236.796800] zocl-drm amba:zyxclmm_drm: swiotlb buffer is full (sz: 1048576 bytes), total 32768 (slots), used 408 (slots)
[  236.797746] [drm:zocl_userptr_bo_ioctl [zocl]] *ERROR* Map SG list failed
[  236.819922] zocl-drm amba:zyxclmm_drm: swiotlb buffer is full (sz: 1048576 bytes), total 32768 (slots), used 408 (slots)
[  236.821733] [drm:zocl_userptr_bo_ioctl [zocl]] *ERROR* Map SG list failed
Resetting rate control (66261 samples)
Resetting rate control (65563 samples)
TEST PASSED
[  493.960032] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 unlocked, ref=0
[  493.989450] [drm] Pid 828 closed device

See the following listing for the three examples launched consecutively:

Results from launching vadd with DATA_SIZE 4096, 65536 and 262144

devmachine# ./app.exe.4096
INFO: Add accelerated vector example
INFO: Found Xilinx Platform
[  140.378345] [drm] Pid 810 opened device
INFO: Loading 'vadd.xclbin'
[  141.881581] [drm] get section AIE_METADATA err: -22
[  141.882261] [drm] zocl_xclbin_read_axlf 66bc6e53-9c1d-4127-b026-d1f6829206f7 ret: 0
[  141.893388] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 locked, ref=1
[  141.895047] [drm] No ERT scheduler on MPSoC, using KDS
[  141.898030] [drm] 8 non-zero interrupt-id CUs out of 9 CUs
[  141.922049] [drm] scheduler config ert(0)
[  141.922246] [drm]   cus(1)
[  141.922397] [drm]   slots(16)
[  141.922489] [drm]   num_cu_masks(1)
[  141.922591] [drm]   cu_shift(16)
[  141.922853] [drm]   cu_base(0x80000000)
[  141.922906] [drm]   polling(0)
[  141.926314] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 unlocked, ref=0
[  141.957888] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 locked, ref=1
[  142.010513] [drm] User buffer is not physical contiguous
TEST PASSED
[  146.330179] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 unlocked, ref=0
[  146.378791] [drm] Pid 810 closed device
devmachine# ls
accelerated_vadd         accelerated_vadd.65536   app.exe.65536
accelerated_vadd.262144  app.exe.262144           vadd.xclbin
accelerated_vadd.4096    app.exe.4096
devmachine# ./app.exe.65536
INFO: Add accelerated vector example
INFO: Found Xilinx Platform
[  155.873463] [drm] Pid 820 opened device
INFO: Loading 'vadd.xclbin'
[  156.335965] [drm] zocl_xclbin_read_axlf The XCLBIN already loaded
[  156.336021] [drm] zocl_xclbin_read_axlf 66bc6e53-9c1d-4127-b026-d1f6829206f7 ret: 0
[  156.347154] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 locked, ref=1
[  156.348152] [drm] Reconfiguration not supported
[  156.348933] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 unlocked, ref=0
[  156.364177] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 locked, ref=1
[  156.395380] [drm] User buffer is not physical contiguous
TEST PASSED
[  220.812880] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 unlocked, ref=0
[  220.841574] [drm] Pid 820 closed device
devmachine# ./app.exe.262144
INFO: Add accelerated vector example
INFO: Found Xilinx Platform
[  236.229053] [drm] Pid 828 opened device
INFO: Loading 'vadd.xclbin'
[  236.692526] [drm] zocl_xclbin_read_axlf The XCLBIN already loaded
[  236.692575] [drm] zocl_xclbin_read_axlf 66bc6e53-9c1d-4127-b026-d1f6829206f7 ret: 0
[  236.705650] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 locked, ref=1
[  236.706336] [drm] Reconfiguration not supported
[  236.708989] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 unlocked, ref=0
[  236.725520] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 locked, ref=1
[  236.753934] zocl-drm amba:zyxclmm_drm: swiotlb buffer is full (sz: 1048576 bytes), total 32768 (slots), used 408 (slots)
[  236.756095] zocl-drm amba:zyxclmm_drm: overflow 0x0000000873069000+1048576 of DMA mask ffffffff bus mask 0
[  236.756350] ------------[ cut here ]------------
[  236.756687] WARNING: CPU: 3 PID: 828 at kernel/dma/direct.c:35 report_addr+0x38/0xa0
[  236.757377] Modules linked in: zocl(O)
[  236.757842] CPU: 3 PID: 828 Comm: app.exe.262144 Tainted: G        W  O      5.4.0-xilinx-v2020.2 #1
[  236.758102] Hardware name: ZynqMP ZCU102 Rev1.0 (DT)
[  236.758233] pstate: 80000005 (Nzcv daif -PAN -UAO)
[  236.758359] pc : report_addr+0x38/0xa0
[  236.758439] lr : report_addr+0x98/0xa0
[  236.758535] sp : ffff800011b0bb10
[  236.758619] x29: ffff800011b0bb10 x28: ffff800011b0bcf8
[  236.758914] x27: 0000000000000018 x26: ffff00087ab0fc00
[  236.759088] x25: ffff0008793d0780 x24: 0000000000000000
[  236.759227] x23: 0000000000000000 x22: ffff00087ab4dc10
[  236.759363] x21: 0000000000100000 x20: ffff00087a31b140
[  236.759443] x19: ffff00087ab4dc10 x18: 0000000000000010
[  236.759524] x17: 0000000000000041 x16: 0000000000000000
[  236.759662] x15: ffff00087a31b568 x14: 616d20414d442066
[  236.759818] x13: 6f20363735383430 x12: 312b303030393630
[  236.760174] x11: 3337383030303030 x10: 3030783020776f6c
[  236.760318] x9 : ffff800011193000 x8 : 0000000000000220
[  236.760464] x7 : 0000000000000006 x6 : 0000000000000001
[  236.760610] x5 : 0000000000000000 x4 : 0000000000000001
[  236.760778] x3 : 0000000000000006 x2 : 9ca27b1d401e1900
[  236.760946] x1 : 9ca27b1d401e1900 x0 : 0000000000000000
[  236.761277] Call trace:
[  236.761342]  report_addr+0x38/0xa0
[  236.762441]  dma_direct_map_page+0x110/0x130
[  236.762571]  dma_direct_map_sg+0x78/0xe0
[  236.763016]  zocl_userptr_bo_ioctl+0x16c/0x2c8 [zocl]
[  236.763185]  drm_ioctl_kernel+0xb8/0x108
[  236.763408]  drm_ioctl+0x200/0x410
[  236.763495]  do_vfs_ioctl+0x878/0xa20
[  236.763625]  ksys_ioctl+0x44/0x90
[  236.763738]  __arm64_sys_ioctl+0x1c/0x28
[  236.763849]  el0_svc_common.constprop.0+0x68/0x160
[  236.763976]  el0_svc_handler+0x6c/0x88
[  236.764049]  el0_svc+0x8/0xc
[  236.764111] ---[ end trace e731bc0ce1c1afd2 ]---
[  236.764900] [drm:zocl_userptr_bo_ioctl [zocl]] *ERROR* Map SG list failed
[  236.796800] zocl-drm amba:zyxclmm_drm: swiotlb buffer is full (sz: 1048576 bytes), total 32768 (slots), used 408 (slots)
[  236.797746] [drm:zocl_userptr_bo_ioctl [zocl]] *ERROR* Map SG list failed
[  236.819922] zocl-drm amba:zyxclmm_drm: swiotlb buffer is full (sz: 1048576 bytes), total 32768 (slots), used 408 (slots)
[  236.821733] [drm:zocl_userptr_bo_ioctl [zocl]] *ERROR* Map SG list failed
Resetting rate control (66261 samples)
Resetting rate control (65563 samples)
TEST PASSED
[  493.960032] [drm] bitstream 66bc6e53-9c1d-4127-b026-d1f6829206f7 unlocked, ref=0
[  493.989450] [drm] Pid 828 closed device

This is certainly not the expected behavior right? The results lead to the following questions which I hope some of the authors/maintainers can help clarify:

• Is this the expected behavior? The accelerated kernel is using const unsigned int. AFAIK and out of #include <limits>, UINT_MAX is 4294967295 which is higher than 262144. Am I missing something?
• How can I engage into debugging this? Intuition tells me that I should start looking at zocl but frankly, I don't have enough experiences yet to have a strong opinion. Can someone more experienced split this to me into reasonable steps he/she would take to debug this?

File not found common/xf_common.hpp when building Runtime_and_System_Optimization/Introduction/design_source/hw_src

Just cloned the repository and was following the first tutorial on Runtime_and_System_Optimization/Introduction.
Edited the config.mk file that looks like

TARGET ?= hw
PLATFORM ?= xilinx_u50_gen3x16_xdma_201920_3
PLATFORM_REPO_PATHS ?= /opt/xilinx/platforms/

It looks like the file common/xf_common.hpp is missing?

$ make
...
INFO: [v++ 60-1315] Creating rulecheck session with output '/opt/Xilinx/Vitis-Tutorials/Runtime_and_System_Optimization/Introduction/design_source/hw_src/_x/reports/resize_rgb/v++_compile_resize_rgb_guidance.html', at Sat Mar 13 20:26:47 2021
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/xilinx_u50_gen3x16_xdma_201920_3.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3/hw/hw.xsa'
INFO: [v++ 74-74] Compiler Version string: 2020.2
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423]   Target device: xilinx_u50_gen3x16_xdma_201920_3
INFO: [v++ 60-242] Creating kernel: 'resize_accel_rgb'
===>The following messages were generated while  performing high-level synthesis for kernel: resize_accel_rgb Log file: /opt/Xilinx/Vitis-Tutorials/Runtime_and_System_Optimization/Introduction/design_source/hw_src/_x/resize_rgb/resize_accel_rgb/vitis_hls.log :
ERROR: [v++ 207-812] 'common/xf_common.hpp' file not found: /opt/Xilinx/Vitis-Tutorials/Runtime_and_System_Optimization/Introduction/design_source/hw_src/resize_rgb.cpp:32:10
ERROR: [v++ 60-300] Failed to build kernel(ip) resize_accel_rgb, see log for details: /opt/Xilinx/Vitis-Tutorials/Runtime_and_System_Optimization/Introduction/design_source/hw_src/_x/resize_rgb/resize_accel_rgb/vitis_hls.log
ERROR: [v++ 60-773] In '/opt/Xilinx/Vitis-Tutorials/Runtime_and_System_Optimization/Introduction/design_source/hw_src/_x/resize_rgb/resize_accel_rgb/vitis_hls.log', caught Tcl error: ERROR: [HLS 207-812] 'common/xf_common.hpp' file not found: /opt/Xilinx/Vitis-Tutorials/Runtime_and_System_Optimization/Introduction/design_source/hw_src/resize_rgb.cpp:32:10
ERROR: [v++ 60-599] Kernel compilation failed to complete
ERROR: [v++ 60-592] Failed to finish compilation
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [resize_rgb.xo] Error 1

Issue: cannot find "Enable platform interfaces"

hi,

On point 5 in "Create Base Vivado Project from Preset" under the tutorial "Vitis-Tutorials/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104/step1" I cannot find the "Platform interfaces" in the Window panel on my VIVADO 2020.2. Is someone has the same problem and he already fixed it? Any idea to find the platform window? I attached a screenshot of my environment.

Convolution-Tutorial: Caught Exception during hw_emu build

Before I start, I will note that I am using the Deployment Target Platofrm version:
xilinx_u250_xdma_201830_2 on my Alveo U250.

When trying to run hardware emulation in this step, I see the following log info:

INFO: [HW-EM 06-0] Waiting for the simulator process to exit
INFO: [HW-EM 06-1] All the simulator processes exited successfully
ERROR: [EMU 60-601]  Exception Caught - Failed with the command REMOVE operation at the Line Number: 1434

I use ctrl+c to kill the process but then I don't get any profiling data when using vitis_analyzer, i.e., there is no Kernel Execution section, or Kernels to Global Memory section.

Any help would be welcome!

How can I get vadd.cpp file?

Hi, I'm just tried Vitis-Tutorials for
getting-started-rtl-kernels.
And Finally I get the xml from VITIS IDE and make XO files, however,
final step, build the Project section. I meet a problem.
my Vitis IDE Problems console makes 2 warnings as follow.

1. No binary containers were found.
2. No host source files were found.

Actually, to create binary container, I cannot understand select icon. cause of no popup from IDE, also no action from IDE. So I did change project configuration setting 2->1. Emulation-HW. and Click Run Configuration on VITIS IDE, but in my case. Arguments tap is empty when i click Arguments tap. It is different status git hub instruction. (it have to be exists u200~ arguments by RTL kernel tutorials,)

So. where can i get vadd.cpp file from you already described on your github tutorials in first page.
or,
If I have to use host.cpp file instead of vadd.cpp file. (supposed your mistake)
How can I make binary container to delete warning.
And how can I add defult setting Argumnts tap as this tutorials?
I hope to check this guide error or my mistake.

Custom on board *.prototxt file for custom yolov4 model

Hi,

I'm trying to running my custom yolov4 model on Ultra96v2, but output boxes is not correct.
I could convert/quantize/compile my custom yolov4 model with Vitisi AI docker ver1.3.411.

After compiling, I got a *.xmodel. I based on below example to create my application on Ultra96v2 target.

• /usr/share/vitis_ai_library/samples/yolov4
• This is from vitis ai runtime 1.3

I reused yolov4_leaky_spp_m.prototxt (from Model Zoo) and modified for my custom yolov4 model to run on board.
My modification is as below.

model {
  kernel {
     mean: 0.0            <-- (1) 3 times, with same value
     scale: 0.00390625    <-- (2) 3 times, with same value
     <snip>
  }
  model_type : YOLOv3
  yolo_v3_param {
    num_classes: 80        <-- (3) change from 80 to 2
    anchorCnt: 3             <-- (4) I don't know, so keep as it is
    layer_name: "160"     <-- (5) 133
    layer_name: "149"     <--     144
    layer_name: "138"     <--     155
    conf_threshold: 0.3
    nms_threshold: 0.45
    biases: 12            <-- (6) I don't know, so keep as it is
    <snip>
    test_mAP: false
  }
}

When I run test_jpeg_yolov4, nothing is outputed. I checked result image, but no box.
Then I reduced conf_threshold to very small 0.001. There are thousand of boxes in result image, but what I want is just 1 box.
Because test image only contains 1 object.
I increase conf_threshold, but i realized that the max conf_threshold when running is 0.00245.
I'm quite confused what is wrong here. Because my float model work well on host PC.

Could you help how to create correct *.prototxt for running on board when user has custom yolov model?

• For above point (3), (4), (5), and (6), how to decide those values?
• For above point (5) and (6), how to decide order values? (since they are same field name)

Thank you very much!

Are there a specific tutorial for a pytorch detection model?

Hello,

I was able to successfully quantize and compile a pytorch classification network by following the instructions of the "PyTorch flow for Vitis AI Tutorial" and the "Vitis AI User Guide". These were my first steps with Vitis-AI.

Now, my goal is to quantize and compile a pytorch object detector network. I generate object detection models with the MMDetection framework, which is an open source object detection toolbox based on PyTorch. I noted that the Vitis Model Zoo includes object detector models for other frameworks as Caffe and Tensorflow. However, I have not found an example of a detector network for PyTorch, which is what I would like to do as my next step. So, I wonder wether pytorch detectors are fully supported by Vitis-AI.

¿Do you know if there are any issues related to pytorch detectors on Vitis? ¿And, do you know if there are a specific tutorial or example of a pytorch detector on Vitis?

Thanks.

How to add the example platforms to Vitis?

How do you add the required platforms to Vitis to be able to run the examples?

ERROR: [v++ 60-1258] No valid platform was found that matches 'zcu102_base'. Please make sure that the platform is specified correctly, and the platform has the right version number. The platform repo paths are:
/xilinx/Vitis/2019.2/platforms
The valid platforms found from the above repo paths are:
/xilinx/Vitis/2019.2/platforms/xcvc1902_fixed/xcvc1902_fixed.xpfm

ERROR: [v++ 60-587] Failed to add a platform: specified platform zcu102_base is not found or is not valid
ERROR: [v++ 60-592] Failed to finish compilation
Makefile:95: recipe for target '_x.sw_emu.zcu102_base/vadd.xo' failed
make: *** [_x.sw_emu.zcu102_base/vadd.xo] Error 1

JRE version is not right

When I use make to compile the sw_emu example, terminal displayed a warning Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist. But my jre version is 11.0.2.
How to set JRE version correctly?
I've tried set the RDI_JAVAROOT environment value.

unable to run hw_emu

Building these tutorials works fine when using sw_emu. But I'm unable to build these applications using hw_emu. I always get the following errors:

Pre-synthesis Control Flow option not available when running C-simulation

While working on the synth and analysis part of the Vitis HLS getting started tutorial I noticed that one of the options has been removed from the C simulation dialog. See the screenshot attached for comparison.

Tutorial:

Current:

Is this option (re)moved?

Version: 2020.2
Build: 3064766

Partitioning Vitis AI SubGraphs on CPU/DPU - EnvironmentNotWritableError

Hi, I'm following Partitioning Vitis AI SubGraphs on CPU/DPU tutorial but stuck at the Install Packages and Patches on the Vitis AI Tools Container step. See screenshot below:

(vitis-ai-pytorch) Vitis-AI /workspace/packages > conda install unilog-1.3.2-h7b12538_35.tar.bz2

Downloading and Extracting Packages
######################################################################################################################## | 100%
Preparing transaction: done
Verifying transaction: failed

EnvironmentNotWritableError: The current user does not have write permissions to the target environment.
environment location: /opt/vitis_ai/conda/envs/vitis-ai-pytorch
uid: 1020
gid: 1023

Can anyone support me with it? Thanks in advanced!

Please recover the links to the Japanese documents urgently.

Hi, It seems the links to Japanese documents are all lost. Could you please recover them urgently as we are planning to use it as a reference for tutorial in a couple of days (August 4th Japan time). This is critical for us. Here are a partial list of the previous URL for Japanese documents. My email address is [email protected].

https://github.com/Xilinx/Vitis-Tutorials/tree/master/docs-jp/docs/vitis-getting-started
https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs-jp/docs/my-first-program/README.md
https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs-jp/docs/my-first-program/cpp_kernel.md
https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs-jp/docs/my-first-program/host_program.md
https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs-jp/docs/my-first-program/building_application.md
https://github.com/Xilinx/Vitis-Tutorials/blob/master/docs-jp/docs/my-first-program/profile_debug.md

Thank you for your quick support.
Yoshihiro Horie, Xilinx Japan

Path to platforms

In the introduction it is written:

To specify the location of the target development platform for Alveo U50 accelerator card, set the following environment variable:

export PLATFORM_REPO_PATHS=<path to platforms>

What is the default path to platforms after default installation?
I wanted to create new Application Project, but there are no platforms to choose from:

AIE/D/01-lenet: makefile and readme needs modification

https://github.com/Xilinx/Vitis-Tutorials/blob/master/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/Makefiles/Makefile

Line 63, SYSROOT_PATH needs to be changed with the path to xilinx-versal-common-v2020.2 at user's end. This should be added to Readme.

Line 247, --package.sd_dir $(PLATFORM_REPO_PATHS)/sw/versal/xrt
This line should be removed?

Line 248-249, the paths need to be changed with the path to xilinx-versal-common-v2020.2 at user's end. This should be added to Readme.

rtl kernel wizard greyed out

Hi,

I try to run one of your example on a zcu 104,

But I cannot start rtl kernel wizard.

Do you know how I can fix this ?

Thank you

Machine_Learning/Design_Tutorials/07-yolov4-tutorial quantize_yolov4.sh error

my environment is
vai_q_tensorflow --version
Vai_q_tensorflow v1.2.0 build for Tensorflow 1.15.2

I am training my own dataset, all is good , I got yolov4-obj_final.weights from yolov4 darknet train process
and convert it to yolov4-obj-new.h5 and tf_model_obj.pb files
in the quantize_yolov4.sh process, I place tf_calib.txt and val2017 folder at the right place and then

./quantize_yolov4.sh
INFO: Checking Float Graph...
Traceback (most recent call last):
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/bin/vai_q_tensorflow", line 11, in
sys.exit(run_main())
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow_core/contrib/decent_q/python/decent_q.py", line 943, in run_main
app.run(main=my_main, argv=[sys.argv[0]] + unparsed)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow_core/python/platform/app.py", line 40, in run
_run(main=main, argv=argv, flags_parser=_parse_flags_tolerate_undef)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/absl/app.py", line 299, in run
_run_main(main, args)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/absl/app.py", line 250, in _run_main
sys.exit(main(argv))
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow_core/contrib/decent_q/python/decent_q.py", line 942, in
my_main = lambda unused_args: main(unused_args, FLAGS)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow_core/contrib/decent_q/python/decent_q.py", line 621, in main
flags.skip_check)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow_core/contrib/decent_q/python/decent_q.py", line 343, in quantize_frozen
check_float_graph(input_graph_def, input_fn, q_config, s_config)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow_core/contrib/decent_q/python/decent_q.py", line 257, in check_float_graph
inputs = input_fn(iter=0)
File "./yolov4_graph_input_keras_fn.py", line 90, in calib_input
custom_image = cv2.resize(image, size, interpolation=cv2.INTER_NEAREST)
cv2.error: OpenCV(4.2.0) /io/opencv/modules/imgproc/src/resize.cpp:4045: error: (-215:Assertion failed) !ssize.empty() in function 'resize'

is the problem caused by tf_calib.txt and val2017 folder, because the content is not from my own data? is this the reason for error , and how to solve this problem, big thanks for advance!

Accuracy drops to 0.1 on ZCU104 : Machine_Learning/Introduction/03-Basic/Module_4/DenseNetX

Hi, I'm trying the tutorial of Machine_Learning/Introduction/03-Basic/Module_4.

After execution the command vai_c_tensorflow at the step6, copied the densenetx.model to ZCU104 board.
I executed 'python3 app_mt.py' at the step 7, the accuracy drops to 0.1 on the ZCU104 board.

root@xilinx-zcu104-2020_2:~/target# python3 app_mt.py
Command line options:
--image_dir : images
--threads : 1
--model : model_dir/densenetx.xmodel
Pre-processing 10000 images...
Starting 1 threads...
FPS=509.41, total frames = 10000 , time=19.6307 seconds
output buffer length: 10000
Correct: 1000 Wrong: 9000 Accuracy: 0.1
root@xilinx-zcu104-2020_2:~/target#

I changed the board to ZCU102, but the result was the same.

The accuracy results of step3(frozen_graph.pb) and step5(quantize_eval_model.pb) seems good, below.
frozen_graph: 0.9306
quantize_eval_model: 0.9265

What could be the reason of the accuracy drop on the board?

Python code for the Post Processing Image of Keras FCN8 UNET segmentation

Hello, I am working with Python and so far following the app_mt.py code, but realized that there is no code to see the post processed image (how the final Segmented Image looks like). There is the code for this in main_mt.cc but I am having problems to pass it to Python. Can I see somewhere the code for this? Or can someone help me?

ERROR when build xo /03-rtl_stream_kernel_integration

When I tried to build xo with the following comment for 03-rtl_stream_kernel_integration project, it had some ERRORs.
How to solve this?
Thanks!

make all_xo TARGET=hw PLATFORM=xilinx_u200_xdma_201830_2

ERROR: [v++ 214-160] in function 'alpha_mix': Local stream 'mixed_img.4' has conflict depth setting (xx/03-rtl_stream_kernel_integration/hw/alpha_mix.cpp:46:61)
ERROR: [v++ 214-160] in function 'alpha_mix': Local stream 'resized_time_img.4' has conflict depth setting (xx/03-rtl_stream_kernel_integration/hw/alpha_mix.cpp:44:61)

Can't run in hw with examples of getting started with rtl kernels

I follow the tutorial of getting started with RTL kernels.
It works fine until building and running example of tutorials in Emulation-HW.
Also it works fine for building example in HW.
However when I run example in HW, it get stucked like below picture.

So I should do xbutil reset for running again this example.

I test various things, and I found that it works fine at ap_ctrl_hls interface, but it didn't work at ap_ctrl_chain interface which this example uses.

Did anyone who follow this example experience this problem?
If yes, how can solve this problem, and what is the cause?

Thank you!

(solved) Why no Vadd_A.sv in the folder

Ok, I found it. It is “Vadd_A_B_example_vadd.sv”

AttributeError: 'NoneType' object has no attribute 'shape'

I am doing the yolov4 tutorial.

when I run the scripts gen_yolo_train_labels.sh I get this error.

I changed the paths of the train and annotations as it says. any help?

Xilinx Vitis vs Vitis HLS

After going through the tutorials for the Xilinx Vitis and Vitis HLS programs I still find vague:

1. What is the conceptual difference?
2. Why are there 2 distinct programs?
3. How do I know which one should I choose?

If I understand it correctly, Xilinx Vitis allows for developing both the software and the firmware (kernel) in the same time within single IDE, whereas Vitis HLS is only for the firmware (kernel) development. Please correct me if I am wrong.

Vitis HLS allows for Vitis Kernel Flow, however the firmware (kernel) can also be implemented in the Xilinx Vitis. Why would someone choose Vitis HLS with Vitis Kernel Flow, if the same can be done in the Xilinx Vitis, plus it has the support also for the software side?

The only clear scenario I can see (although I am not 100 % sure), is that when someone wants to generated IP for the use with the Vivado, then choosing Vitis HLS with the Vitis IP Flow is the only way to go.

Accuracy drops to 0.098 on ZCU102 : Machine_Learning/Design_Tutorials/02-MNIST_classification_tf

Hello. I am trying to deploy MNIST classification example on ZCU102 board but the accuracy drops to 0.098. Can you please consider this issue?

Issues building kernels - results make no sense

I was doing some tests with more complex kernels and XRT but things started failing. After debugging things for a few days I realized that I couln't eve reproduce the simplest examples (e.g. vadd) so I came back to https://github.com/Xilinx/Vitis-Tutorials/blob/master/Getting_Started/Vitis/ (that's how I bumpd into #69 and #70). As of now, I'm unable to reproduce vadd simple Getting Started Vitis tutorial. Kernel's result makes no sense to me so I though I'd share with those of you much more experienced:

./app.exe vadd.xclbin
[  183.410540] [drm] Pid 1191 opened device
[  183.414484] [drm] Pid 1191 closed device
INFO: Found Xilinx Platform
[  183.443262] [drm] Pid 1191 opened device
[  183.449404] [drm] Pid 1191 closed device
[  183.453381] [drm] Pid 1191 opened device
INFO: Loading 'vadd.xclbin'
[  184.938156] [drm] get section AIE_METADATA err: -22
[  184.938189] [drm] zocl_xclbin_read_axlf 1254ea14-6c9a-0ebc-fddd-89abec916d44 ret: 0
[  184.945489] [drm] bitstream 1254ea14-6c9a-0ebc-fddd-89abec916d44 locked, ref=1
[  184.953169] [drm] No ERT scheduler on MPSoC, using KDS
[  184.965519] [drm] 8 non-zero interrupt-id CUs out of 9 CUs
[  184.965568] [drm] scheduler config ert(0)
[  184.971044] [drm]   cus(1)
[  184.975050] [drm]   slots(16)
[  184.977745] [drm]   num_cu_masks(1)
[  184.980704] [drm]   cu_shift(16)
[  184.984183] [drm]   cu_base(0x80000000)
[  184.987404] [drm]   polling(0)
[  184.991260] [drm] bitstream 1254ea14-6c9a-0ebc-fddd-89abec916d44 unlocked, ref=0
Error: Result mismatch
i = 16 CPU result = 6296 Device result = 0
TEST FAILED
[  184.995599] [drm] bitstream 1254ea14-6c9a-0ebc-fddd-89abec916d44 locked, ref=1
[  185.025175] [drm] bitstream 1254ea14-6c9a-0ebc-fddd-89abec916d44 unlocked, ref=0

I reproduced my setup a few times (which took me a few hours) to ensure I wasn't just distracted. Has anyone bumped into something similar? As of my last tests, I tried modifying the kernel's simple source code for returning a fixed constant or other sums but I'm still getting the same result, 0.

My setup:

setup XRT

cd /home/erle/Desktop/Xilinx; git clone https://github.com/Xilinx/XRT
cd XRT; sudo src/runtime_src/tools/scripts/xrtdeps.sh  # install dependencies
source /tools/Xilinx/Vitis/2020.2/settings64.sh  # necessary for ERT
export PATH="/usr/bin":$PATH  # FIXME: adjust path for CMake 3.5+
cd build; ./build.sh
cd Release; sudo apt-get install ./xrt_*-amd64-xrt.deb

Fetch Vitis-Tutorials

cd ~; git clone https://github.com/Xilinx/Vitis-Tutorials

set environment

Requires to first fetch rootfs and sysroots from here, while putting it into a coherent folder-structure. Then:

cd ~/Vitis-Tutorials/Getting_Started/Vitis/example/zcu102/hw/
source /tools/Xilinx/Vitis/2020.2/settings64.sh
source /opt/xilinx/xrt/setup.sh
unset LD_LIBRARY_PATH
export PLATFORM_REPO_PATHS="/home/erle/Desktop/Xilinx/xilinx_zcu102_base_202020_1"
export ROOTFS=/home/erle/Desktop/Xilinx/rootfs 
source /home/erle/Desktop/Xilinx/rootfs/ir/environment-setup-aarch64-xilinx-linux

build the example

${CXX} -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++
v++ -c -t hw --config ../../src/zcu102.cfg -k vadd -I../../src ../../src/vadd.cpp -o vadd.xo 
v++ -l -t hw --config ../../src/zcu102.cfg ./vadd.xo -o vadd.xclbin
v++ -p -t hw --config ../../src/zcu102.cfg ./vadd.xclbin --package.out_dir package --package.rootfs ${ROOTFS}/rootfs.ext4 --package.sd_file ${ROOTFS}/Image --package.sd_file xrt.ini --package.sd_file app.exe --package.sd_file vadd.xclbin --package.sd_file run_app.sh

Gprof

I followed all steps given in convolution tutorial executed the executable file convolve as given but while executing the gprof command
gprof convolve gmon.out> gprofresult.txt
I get this
gmon.out: No such file or directory

Where I am going wrong?

07-yolov4-tutorial/scripts > ./compile_yolov4.sh error

hello, I am using vitis-ai 1.3 to try the tutorial 07-yolov4-tutorial, but when I execute compile_yolov4.sh the error bellow occurred, what could be the reason and how to solve it? thanks very much~

before the step execute compile_yolov4.sh, I have generated tf_model.pb and yolov4_quantized folder(containing deploy_model.pb quantize_eval_model.pb ) successfally.
besides, I have changed the compile_yolov4.sh because the vitis-ai1.3 has changed json file path accordingly.

TARGET=ZCU102
NET_NAME=yolov4

ARCH=${CONDA_PREFIX}/arch/DPUCZDX8G/${TARGET}/arch.json

(vitis-ai-tensorflow) Vitis-AI /workspace/888888/07-yolov4-tutorial/scripts > ./compile_yolov4.sh

---

• VITIS_AI Compilation - Xilinx Inc.

---

[INFO] Namespace(inputs_shape=None, layout='NHWC', model_files=['../yolov4_quantized/deploy_model.pb'], model_type='tensorflow', out_filename='../yolov4_compiled//yolov4_org.xmodel', proto=None)
[INFO] tensorflow model: ../yolov4_quantized/deploy_model.pb
[INFO] parse raw model : 0%| | 1/407 [00:00<00:00, 1246.45it/s]
Traceback (most recent call last):
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/bin/xnnc-run", line 33, in
sys.exit(load_entry_point('xnnc==1.3.0', 'console_scripts', 'xnnc-run')())
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/main.py", line 194, in main
normal_run(args)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/main.py", line 178, in normal_run
in_shapes=in_shapes if len(in_shapes) > 0 else None,
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/xconverter.py", line 131, in run
xmodel = CORE.make_xmodel(model_files, model_type, _layout, in_shapes)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/core.py", line 104, in make_xmodel
model_files, layout, in_shapes=in_shapes, model_type=model_t
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/translator/tensorflow_translator.py", line 97, in to_xmodel
model_name, raw_nodes, layout, in_shapes, model_fmt, model_type
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/translator/tensorflow_translator.py", line 161, in create_xmodel
xmodel = cls.__create_xmodel_from_tf1(name, layers, layout, in_shapes)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/translator/tensorflow_translator.py", line 243, in __create_xmodel_from_tf1
xmodel_name, layout, layers, const_layer_dict, super_const_dict, in_shapes
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/xnnc/translator/tensorflow_translator.py", line 1847, in __generate_xmodel
), f"[ERROR] TF Conv2d requires two inputs: actual: {bottom}."
AssertionError: [ERROR] TF Conv2d requires two inputs: actual: ['image_input'].

Yolov4 using VOC Data Set and converting to Caffe Tutorial

set number of classes to 20 for each output layer
set filter size of convolutional layer before each output layers to 75

how to set classes and filter.

I cant run bash scripts/run_vai_c_zu104.sh success .

GS/Vitis/ZCU102: makefile needs modification

https://github.com/Xilinx/Vitis-Tutorials/blob/master/Getting_Started/Vitis/example/zcu102/hw/Makefile

(Original)
package/sd_card.img: app.exe vadd.xclbin xrt.ini run_app.sh
$(call ndef,ROOTFS)
v++ -p -t ${TARGET} --config ../../src/zcu102.cfg ./vadd.xclbin -o vadd.xclbin
--package.out_dir package
--package.rootfs ${ROOTFS}/rootfs.ext4
--package.sd_file vadd.xclbin
--package.sd_file ${ROOTFS}/Image
--package.sd_file xrt.ini
--package.sd_file emconfig.json
--package.sd_file app.exe
--package.sd_file run_app.sh

(Modified)
package/sd_card.img: app.exe vadd.xclbin xrt.ini run_app.sh
$(call ndef,ROOTFS)
v++ -p -t ${TARGET} --config ../../src/zcu102.cfg ./vadd.xclbin
--package.out_dir package
--package.rootfs ${ROOTFS}/rootfs.ext4
--package.sd_file vadd.xclbin
--package.sd_file ${ROOTFS}/Image
--package.sd_file xrt.ini
--package.sd_file app.exe
--package.sd_file run_app.sh

Segmentation faults on cpu_src in Hardware_accelerators/Introduction/03

I get a segmentation fault at runtime on the baseline CPU program. Any clues?

aarch64-xilinx-linux-g++ missing, using aarch64-linux-gnu-g++ instead

Connected to #69.

The instructions at https://github.com/Xilinx/Vitis-Tutorials/blob/master/Getting_Started/Vitis/Part4.md read as:

...
$(CXX) -Wall -g -std=c++11 ../../src/host.cpp -o app.exe -I/usr/include/xrt -lOpenCL -lpthread -lrt -lstdc++
...

cross-compilation wont' work this way since CXX contains the following in my environment with Vitis 2020.2:

echo $CCX
aarch64-xilinx-linux-g++ -march=armv8-a+crc -mtune=cortex-a72.cortex-a53 --sysroot=/tools/Xilinx/Vitis/2020.2/data/emulation/qemu/unified_qemu_v5_0/sysroots/aarch64-xilinx-linux

aarch64-xilinx-linux-g++ is nowhere to be found in my file system. Instead, I used aarch64-linux-gnu-g++ to successfully cross-compile things.

Edit: I was wrong, I did find aarch64-xilinx-linux-g++ after doing a better search.