zicog / xoro

A picorv32 RISC-V processor with some very simple memory and peripherals. For Terasic DE-0 Nano

xoro

This is the picorv32 RISC-V processor in Verilog wrapped in some very simple memory and peripherals. Enough to get it working on a Terasic DE-0 Nano Cyclone IV FPGA board.

The name comes from the fact that this project grew out of a version of the xoroshiro128+ pseudo random number generator in Verilog.

picorv32 is by Clifford Wolf : https://github.com/cliffordwolf/picorv32

Building the firmware

The current firmware is very simple and only prints "Hello World!" repeatedly to the UART at 38400 baud. If you want to tinker with it it can be rebuild with:

$ make firmware/firmware.hex

Run on DE0 Nano board.

Just open the project file xoro.qpf in Quartus.

Hit the "Start compilation" button.

When it's done hit the "Programmer" button. Select the xoro.sof file from the out_put files directory and hit start.

To see the UART output I use a Parallax Prop Plug serial to USB adapter.See pin assignments to see where to plug it in to the header.

Run under Icarus simulator

Build the top level test bench with iverilog:

$   iverilog -o xoro_top_tb.vvp test_bench/xoro_top_tb.v rtl/xoro_top.v rtl/memory.v rtl/gpio.v rtl/prng.v  \
    rtl/uartTx.v rtl/xoroshiro128plus.v rtl/picorv32.v rtl/address_decoder.v rtl/timer.v

And run under the Icarus simulator:

$ vvp xoro_top_tb.vvp

This produces a ton of output so maybe you want:

$ vvp xoro_top_tb.vvp | less

Or redirect to a file:

$ vvp xoro_top_tb.vvp > test.txt

In order to understand the output you will need to know what firmware it is executing. A disassembled listing can be obtained with objdump:

$ riscv32-unknown-elf-objdump -d firmware/firmware.elf

xoro's Issues

Problems compiling quartus project

Hi! I am trying to compile the project for a De0-nano board following the instructions. Nevertheless, quartus can't compile the project, here is the messages that I get:

Info (12128): Elaborating entity "Memory" for hierarchy "Memory:mem"
Error (10054): Verilog HDL File I/O error at memory.v(32): can't open Verilog Design File "Memory.v_toplevel_memory_1_symbol0.bin"
Error (10054): Verilog HDL File I/O error at memory.v(33): can't open Verilog Design File "Memory.v_toplevel_memory_1_symbol1.bin"
Error (10054): Verilog HDL File I/O error at memory.v(34): can't open Verilog Design File "Memory.v_toplevel_memory_1_symbol2.bin"
Error (10054): Verilog HDL File I/O error at memory.v(35): can't open Verilog Design File "Memory.v_toplevel_memory_1_symbol3.bin"
Error (12152): Can't elaborate user hierarchy "Memory:mem"
Info (144001): Generated suppressed messages file E:/xoro-master/output_files/xoro.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 5 errors, 38 warnings
Error: Peak virtual memory: 4774 megabytes
Error: Processing ended: Fri Aug 13 17:12:30 2021
Error: Elapsed time: 00:00:10
Error: Total CPU time (on all processors): 00:00:21

I am using Quartus Prime Lite Edition 18.0. It seems to me that the top module is not pointing to the memory properly, I mean that it seems that the memory is not synthesizable. Am I right ? If not, could you please tell me what I am doing wrong ?

Thanks in advance