zicog / xoro Goto Github PK

Hi! I am trying to compile the project for a De0-nano board following the instructions. Nevertheless, quartus can't compile the project, here is the messages that I get:

Info (12128): Elaborating entity "Memory" for hierarchy "Memory:mem"
Error (10054): Verilog HDL File I/O error at memory.v(32): can't open Verilog Design File "Memory.v_toplevel_memory_1_symbol0.bin"
Error (10054): Verilog HDL File I/O error at memory.v(33): can't open Verilog Design File "Memory.v_toplevel_memory_1_symbol1.bin"
Error (10054): Verilog HDL File I/O error at memory.v(34): can't open Verilog Design File "Memory.v_toplevel_memory_1_symbol2.bin"
Error (10054): Verilog HDL File I/O error at memory.v(35): can't open Verilog Design File "Memory.v_toplevel_memory_1_symbol3.bin"
Error (12152): Can't elaborate user hierarchy "Memory:mem"
Info (144001): Generated suppressed messages file E:/xoro-master/output_files/xoro.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 5 errors, 38 warnings
Error: Peak virtual memory: 4774 megabytes
Error: Processing ended: Fri Aug 13 17:12:30 2021
Error: Elapsed time: 00:00:10
Error: Total CPU time (on all processors): 00:00:21

I am using Quartus Prime Lite Edition 18.0. It seems to me that the top module is not pointing to the memory properly, I mean that it seems that the memory is not synthesizable. Am I right ? If not, could you please tell me what I am doing wrong ?

Thanks in advance