We are looking for a 68k design that we can put into an FPGA that would be shipped
in a commercial product.

We'd like to use this design but can't until we understand the license terms.

thanks

the altsyncram module used in ao68000 is only available on Altera. It would be preferable to have a custom memory module that instantiated the correct memory depended on the platform.

ao68000.v line 2841 shows result assigned with a non-blocking assignment.

a068000.v line 2852 shows result assigned with a blocking assignment.

I don't know what that the Altera synthesizer does with mixed assignment like this
but Xilinx XST will fail and report an error.

This occurs in many places and I am sure that if this design ran on an Altera DE2-70
then the synthesizer resolved it in a consistent manner.

I could make them consistent in the source but I need to know what behavior is intended in the
design.

thanks,
Aaron Boxer

If the CPU writes to an address which has already been prefetched it should flush the prefetch cache. Otherwise unknown behaviour occurs.

reproduced using ao68000 to run the atari operating system TOS1.04

Patch below... line numbers may be wrong...

Index: C:/Users/Stephen/Documents/Xilinx/AtariST/ao68000.v

--- C:/Users/Stephen/Documents/Xilinx/AtariST/ao68000.v (revision 30)
+++ C:/Users/Stephen/Documents/Xilinx/AtariST/ao68000.v (working copy)
@@ -1136,6 +1136,14 @@
CYC_O <= 1'b1;
ADR_O <= address_i[31:2];
STB_O <= 1'b1;

•                           if ((address_i - pc_i) <= 8) begin
  

•                               prefetch_ir_valid_32_o <= 1'b0;
  

•                               prefetch_ir_valid_o <= 1'b0;
  

•                               prefetch_ir_valid_80_o <= 1'b0;
  

•                           end
  
                   if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
                       DAT_O <= { 16'b0, data_write_i[31:16] };