bnossum / midgetv

rv32i/rv32im/rv32imc for iCE40. Wishbone interface.

midgetv

midgetv is a RISC-V implementation written specifically for ice40* FPGAs. The base ISA is RV32I. Standard extensions Zicsr and Zifencei are always included. Standard extension C, M can be compiled in.

midgetv uses Wishbone b4 for interconnect.

To use midgetv

Include midgetv.v into your project, and instantiate m_midgetv_core. The program to run on the core is given by parameters prg00 through prg0F, usually generated by transforming a binary RISC-V program with the utility midgetv_bin2ebr.

More (rather unstructured) information is available here.

Semantic Versioning API specification

1. Signal interface to module m_midgetv_core is part of the API.
2. The coarse memory map of midgetv is part of the API.
3. The way a binary file is mapped to localparam specifications by the utility midgetv_bin2ebr is part of the API.

midgetv's Issues

Minor errors in instruction decode

The test program m_ucodepc.bin traverses all RV32I OpCodes, and give a fair indication on whether the handwritten microcode for the different OpCodes are located at the correct place. While all used OpCodes seems to be at the right place, there are a number of locations in the microcode store (that were thought to be accessible by unsupported Opcodes) that are never hit, hence free for use. Conversely, there are a number of microcode instructions (in the middle of a sequence) that can actually be hit by unsupported Opcodes. Here there is some reorganization to be done. Details:

0x22 should be unreachable from decode, but is hit 4194304 times
0x2e reserved for illegal OpCode, but is infact never hit
0x42 should be unreachable from decode, but is hit 4194304 times
0x4e reserved for illegal OpCode, but is infact never hit
0x62 should be unreachable from decode, but is hit 4194304 times
0x6e reserved for illegal OpCode, but is infact never hit
0x82 should be unreachable from decode, but is hit 4194304 times
0x8e reserved for illegal OpCode, but is infact never hit
0xa2 should be unreachable from decode, but is hit 4194304 times
0xc2 should be unreachable from decode, but is hit 4194304 times
0xce reserved for illegal OpCode, but is infact never hit
0xe2 should be unreachable from decode, but is hit 4194304 times
0xee reserved for illegal OpCode, but is infact never hit

Save 1 SB_LUT when rinstret counter is omitted from the design

Regardless of whether the retired instruction counter is implemented or not, a duplicate of carry-out of the ALU is present. This should be suppressed if the retired instruction counter is not used in the microcode.

Value in `mtval` is wrong when execution proceeds into an illegal section.

When linear execution (no branches) of instructions "falls over the edge" into a region that can't contain code, the fetch access fault is correctly triggered. However, mtval will not hold the correct address.

Example iceblink40-hx1k placement internal error with iCECube2 in a specific case

Using release 0.1.2-bugexpose, using iCECube2 with Lattice LSE as a synthethis tool,
the following error occurs in placement:
Internal Error: Assumption 'pBInfo->GetDFFGroup() == plBlockInfo::NO_GROUP || mDffGrp == pBInfo->GetDFFGroup()' failed in plCLBCluster.cpp line 368

This only happens when LAZY_PLACEMENT == 2, (and HIGHLEVEL = 1).
The error disappears if the placement chained-lut specifications are removed.

Minor error in Makefile for morse.S

Due to lousy syntax, and renaming of tsthw to hwtst, build of morse.S must be done by hand.

Does not obey Wishbone rule 3.55

RULE 3.55

MASTER interfaces MUST be designed to operate normally when the SLAVE interface
holds [ACK_I] in the asserted state.

This is not the case for midgetv now.

EBR connection errors when using more than 2 EBRs

When instantiating midgetv with more than 1 KiB EBR, simulation passes, but this fails on hardware.

t181.S fails slightly

t181.S is a test program that checks the csrrw instruction. As part of the test, register mepc is read without prior being written. It was thought that mepc would have a definite value at startup in midgetv, but presently it can have at least 3 distinct values at start-up depending on options in the core. This is what breaks t181.S

Too permisive instruction decode for many instructions

Instructions slli, srli, add, sll, slt, sltu, xor, srl, or, and and should only be valid when funct7 == 7'b00000000. Presently funct7 is mostly ignored in decode of these instructions.

Likewise, srai, sub, and sra should only be valid when funct7 == 7'b0100000. funct7 is mostly ignored also here.

ecall should only be decoded when field rs1 and rd are 5'b00000, and imm12 == 12'h0. This is presently not the case. Only imm12[1:0] is used in the decode.

Likewise, ebreak should only be decoded when field rs1 and rd are 5'b00000, and imm12 == 12'h1. While the whole of imm12 is used in this decode, fields rs1 and rd are presently ignored.

WFI fails

WFI should be implemented as NOP but is interpreted as EBREAK. See test program sw/first/t187.S.

Illegal opcodes xxxx500f wrecks midgetv

Opcodes of this form is not detected as illegal, and is erroneously decoded.

Possible startup condition problem

The morse program will sometimes (not often) fail to load on the iceblink40-1khx board. This may be because of a clock startup problem on my particular board, but may also indicate a start-up condition that is not considered. More investigation is needed

iCECube2 with Synplify Pro as synthetis tool fails to compile examples

Using release 0.1.2-bugexpose: For both the upduino and iceblink40-hx1k example project, using Synplify Pro fails during compile, with the following error:

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 139MB)
Writing EDIF Netlist and constraint files
@n: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@n: BW107 |Synopsys Constraint File capacitance units using default value of 1pF `

'@n: FX1056 |Writing EDF file: /home/bnossum/GITSTUFF/GIT/midgetv/tsthw/upduino2 /iCEcube2_flow/iCEcube2_flow_Implmnt/iCEcube2_flow.edf`

@W: FX708 |Found invalid parameter 64
While running 64-bit - Linux build
@e::Signal 011 error in m_generic
Stack trace`

===========
0x19d922e
0x19daae0
0x19dac87
0x7f066201c38f
0x7f06614b46cc
0xa4cbb3
0xa670ee
0x69091f
0x69147e
0xe1c4c5
0x161c107
0x161e1d4
0xe2035b
0xe2298e
0xe54011
0xe63d55
0x43d3e1
Please open a web case about this problem. A Synopsys CAE will then contact you.`

mcycle reset at taken branch

mcycle is updated at each OpCode fetch, but when a branch is taken it is reset.

`ECALL` and `EBREAK` increments `minstret`

From Volume II: RISC-V Privileged Architectures V1.12-draft:
"As ECALL and EBREAK cause synchronous exceptions, they are not considered to retire, and should not increment the minstret CSR."
Midgetv do not special-case these instructions.

rv32i too lax in instruction decoding

In release 2.2.1, compiled as core rv32i: Instructions for rv32im should lead to illegal instruction exception.

in SB_RAM40_4K instanses. Consider change from RE/WE to RCLKE/WCLKE

Rather belatedly I saw a reference to a a silicon bug, YosysHQ/yosys#101. It seems that one should use RCLKE/WCLKE instead of RE/WE because mem[0] can (sometimes) be written to 0 after configuration but before release of the iCE40.