cnrv / cnrv-fpu Goto Github PK

• Both blank and TAB are used. Recommend to replace all TABs to blanks.
• Parameters are both declared along with module definition and within it. Recommend to replace the internal ones to localparams.
• DesignWare files (lza, lzd) are used in rtl files. Not really sure whether these DW files are used? If yes, we probably need to replace them with generic implementations to avoid License issues.
• DesignWare components are used in testbenches. This could potentially cause License issues and stop people, who do not have access to Synopsys, from using the design. For this problem, I suggest to use testfloat running in C/C++ and communicating with Verilator using DPI interface. I have used this for lowRISC and it seems compatible with most EDA tools and relatively stable.
• Need travis-ci to run checks at background. This also depends on running Verilator as opensource substitute for VCS.

Can you provide proper document fp_mac in english.

• Having two testbench directories is a bit confusing
• Tried to compile them with Synopsys DC but I get a lot of errors and warnings
• Can you separate each module in a separate file
• Having some Nakefiles for verilator would be good too
• what is different from the jm2000 duplicate project ?