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Home Page: http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-15-introducing-rpu/
License: Apache License 2.0
Basic RISC-V CPU implementation in VHDL.
Home Page: http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-15-introducing-rpu/
License: Apache License 2.0
Hey! I've been following this project for quite some time, and it was a huge inspiration for building my own RISC-V CPU. However, one issue I've always had when looking at the sources here is that I just can't figure out a way to get consistent and correct indentation and alignment. There is a wild mix of spaces and tabs, but no single tab width seems to match what you must be looking at, not even in single files! If you have some special editor config for your tab stops, do tell (and maybe document it somewhere). Otherwise, I'd gladly reformat everything to be consitent, I just need to know what indentation mode you want (personally I'm a "tabs for indentation, spaces for alignment" guy, but that's a matter of taste).
I was trying to read the previous RISC-V CPU in VHDL posts, but all I got was 404 not found!
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