isabella232 Goto Github PK

riscv-linux

RISC-V Linux Port

riscv-llvm

SiFive's LLVM working tree

riscv-newlib

RISC-V port of newlib

riscv-opcodes

RISC-V Opcodes

riscv-openocd

Fork of OpenOCD that has RISC-V support

riscv-p-spec

RISC-V Packed SIMD Extension

riscv-pk

RISC-V Proxy Kernel

riscv-platform-specs

RISC-V Profiles and Platform Specification

riscv-plic-spec

PLIC Specification

riscv-port

https://openjdk.java.net/projects/riscv-port

riscv-profiles

RISC-V Architecture Profiles

riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support

riscv-semihosting-spec

riscv-smbios

RISC-V SMBIOS Type 44 Spec

riscv-software-list

The RISC-V software tools list, as seen on riscv.org

riscv-state-enable

riscv-test-env

riscv-tests

riscv-time-compare

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

riscv-zawrs

The repo will be used to hold the draft Zawrs (fast-track) extension and to make releases for reviews. The Zawrs extension defines a single instruction to be used in polling loops that allows a core to enter a low-power state and wait on either a write to a memory location or other asynchronous system events. It addresses common use-cases in operating systems when waiting for contended locks or for completion events signaled by external I/O agents, accelerators, and other peripherals.

riscv-zfinx

riscv32-code-density-test-bench

Density test bench for RISCV - "Compress extension"

riscvspecformal

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

risev2g

Risev2g project

risk-management-framework

ATO framework

riskassessmentframework

The Secure Coding Framework

risky

A lightweight Ruby ORM for Riak

rism

risque-bower