lowrisc / rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC). DEPRECATED in favour of the OpenTitan PLIC: https://github.com/lowRISC/opentitan/tree/master/hw/ip/rv_plic

Deprecated

This repository has been archived. Please refer to the OpenTitan PLIC instead.

RISC-V Platform-Level Interrupt Controller

RV_PLIC module is to manage multiple interrupt events generated from the peripherals. It implements Platform-Level Interrupt Controller in RISC-V Privileges specification Section 7.

reg_rv_plic.py

The tool is to create register hjson file given values of number of sources, number of targets, and max value of priority. By default target is 1 and priority is 7 (8 level of priorities supported)

To change the value and to re-create hjson,

$ reg_rv_plic.py -s 64 -t 2 -p 15 rv_plic_reg.tpl.hjson > rv_plic_reg.hjson

rv_plic's Issues

Simultaneous interrupts

On Ariane, the CPU ceases to respond to interrupts after a while, and I am testing the hypothesis that it is the simultaneous arrival of multiple interrupts that is causing the problem. I attach a waveform captured from the hardware under this circumstance for further study. To save memory, only the portion of the waveform with req_i.valid high is captured. Let me know if an alternative arrangement would be more useful.

plic.zip

@zarubaf @eunchan @asb