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View Code? Open in Web Editor NEWTracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
Home Page: https://riscv.org/
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
Home Page: https://riscv.org/
References to beginner and intermediate level resources are broken
OpenSecurityTraining2 Architecture 1005: RISC-V Assembly
[extracted from their linkedin announcement post]
The class covers the RISC-V RV32I/RV64I base ISAs, the "C" Compressed instructions, and the "M" multiply/divide/remainder extensions.
The class also includes the CMU binary bomb lab, running in a RISC-V QEMU VM. AND as a special bonus, it includes a sneak peek at the Ghidra-for-debugging class material!
This class takes ~28 hours on average (not counting the binary bomb lab, or optional Ghidra installation & setup time.)
[this part I wrote myself]
The content is free and very hands-on, you're expected to actually run risc-v code and follow the execution with GDB, and there are multiple rounds of randomly generated assembly challenges for you to "run" and find the final result.
https://p.ost2.fyi/courses/course-v1:OpenSecurityTraining2+Arch1005_IntroRISCV+2024_v1/course/
C programming language experience is expected
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Building a RISC-V CPU core - Steve Hoover
This free EdX course by Steve Hoover (founder of Redwood EDA) is a great way for a beginner to get started with digital logic design and basic RISC-V microarchitecture design with the help of modern, freely available open source tools such as the Makerchip IDE all from the convenience of your browser. This course provides a hands on experience with the RISC-V ISA and modern open-source logic design tools which utilize the features of a powerful and emerging HDL, Transaction-Level Verilog, designed by Redwood EDA.
No prerequisites required, this course covers all the basics from scratch, although an introductory knowledge on what RISC-V is would be helpful.
This course is a beginner level course, it's best suited for enthusiasts with minimal exposure to Digital Design and Computer Architecture.
Ajith P V, [email protected]
It would be better to add one more section for some of the best visual tools that helps to understand the RISC-V in a better way.
These tools can be used during the beginner or intermediate tutorials to get the visualization of the RISC-V ISA.
Example:
emulsiV:
emulsiV is a visual simulator for a simple RISC processor called Virgule.
Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, “minimal” means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program.
RISC-V Instruction Encoder/Decoder:
This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other.
Tutorial: RISC-V Vector Extension Demystified [Andes]
A very in-depth, three hour long video introduction to the RISC-V Vector extension.
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Computer Architecture- A Quantitative Approach-6th Edition, by David A. Patterson and John L. Hennessey
Covers advanced computer architecture concepts pertaining to high performance computing principles and domain specific architectures along with examples and exercises pertaining to the RISC-V ISA-(6th Edition onwards). This is a step-up from the first book,(Hardware-Software Interface), with advanced concepts like Instruction , Data and Thread Level Parallelism along with introduction to Vector, SIMD and GPU architectures.
It also continues the tradition of using real-world examples to demonstrate the concepts, by introducing memory organizations and architectures of ARM Cortex A8, Intel Core i7, Nvidia GTX-280 GPUs and so on.
Prerequisites : Digital Design, Basic Computer Architecture Concepts, and introductory knowledge on the RISC-V ISA.
The reader is recommended to finish the Computer Organization and Design -Hardware Software Interface-RISC-V edition first, before moving forward with this book.
This book is generally preferred for Master Students, so I would suggest to keep this resource in the Advanced resource section after the Intermediate stage. This book could still be included in the intermediate section, but the Hardware Software Interface is a necessary prerequisite to have a clear understanding of the concepts.
Step-by-step RISC-V C Compiler development
This MOOC is an online educational course that teaches how to develop a simple RISCV C language compiler from scratch step by step.
The video of this course is at: https://www.bilibili.com/video/BV1gY4y1E7Ue
The sample code of this course is at: https://github.com/sunshaoce/rvcc
The teaching resources of this course is at: https://github.com/sunshaoce/rvcc-course
https://www.bilibili.com/video/BV1gY4y1E7Ue
Videos, slides, sample codes and comments are all in Chinese.
For more information please contact MOOC author: Shao-Ce SUN [email protected]
github id: https://github.com/sunshaoce
Step by step development of a RISC-V operating system
This MOOC is an online education course that introduces the relevant knowledge of riscv and teaches how to develop a simple riscv operating system from scratch step by step.
The video of this course is at: https://www.bilibili.com/video/BV1Q5411w7z5
The teaching resources and sample code of this course are at: https://github.com/plctlab/riscv-operating-system-mooc
This MOOC has been very popular since it was launched in the spring of 2021.
https://github.com/plctlab/riscv-operating-system-mooc
Videos and slides are in Chinese, sample codes and comments are in English.
For more information please contact MOOC author: Chen Wang [email protected]
github id: https://github.com/unicornx
RVfpga 3.0: Understanding Computer Architecture
The RVfpga Course in Computer Architecture provides hands-on understanding of a commercial RISC-V processor, RISC-V SoC, and the RISC-V ecosystem. Specifically, the RVfpga v3.0 course shows how to target a VeeR EL2 and a VeeR EH1 based system-on-chip (SoC) to 3 different FPGA boards: the Digilent Basys 3 board ($124 academic price), the Real Digital Boolean board ($74 academic price), and the Digilent Nexys A7 board ($262 academic price). The course can also be completed only in simulation; for that purpose, several simulation tools are provided which enable the user to simulate the system at different levels: from a Boolean/Nexys A7/Basys 3 virtual board down to the VeeR EH1/EL2 pipeline.
https://university.imgtec.com/rvfpga-el2-v3-0-english-downloads-page/
Expected Prior Knowledge:
– Digital design
– High-level programming (preferably C)
– Instruction set architecture / assembly programming
– Microarchitecture
– Memory systems
All this material is covered in Digital Design and Computer Architecture: RISC-V Edition, Harris & Harris, Elsevier 2021.
Please contact with Daniel Chaver at [email protected] for any questions or comments.
CREATOR
CREATOR is a didactic simulator that allows the development, simulation, and debugging of RISC-V (RV32IMFD) assembly programs intuitively and interactively. It is a web application, so it can be used on any type of device (desktop, tablet, smartphone, etc.) without installing additional software, only a modern web browser (Google Chrome, Mozilla Firefox, Apple Safari, etc.) is required.
For more information: https://creatorsim.github.io/
https://creatorsim.github.io/creator/
We have seen issue #9 , if a new category of visual tools is added, CREATOR we believe fits in this category. Otherwise, we believe that it fits in the section "Intermediate-Level resources"
Tiny-asm
Tiny-asm is a standard C RISCV assembler derived from GNU gas. It is very small and easy to compile and install, since it consists of only 2 files: asm.c and asm.h. It is in
https://github.com/jacob-navia/tiny-asm.git
This repository includes the documentation.
https://github.com/jacob-navia/tiny-asm.git
If you want to tinker with the assembler you have to know the C language.
The documentation is in English
Yoiu can compile the assembler in any machine that supports standard C.
For more information, donations, whatever:
[email protected]
QtRvSim - RISC-V CPU Simulator with Cache and Pipeline Visualization
QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. The project page https://github.com/cvut/qtrvsim/ provides links to GNU/Linux, Mac OS and Windows native binaries. Online version and related courses materials are available at https://comparch.edu.cvut.cz/ . It provides enough subsystems to run, port or implement a simple (no memory protection or paging; M-mode only) operating system with preemptive multitasking.
https://github.com/cvut/qtrvsim
Basic or intermediate, ideal companion tool to Computer Organization and Design RISC-V edition: The Hardware Software Interface textbook.
Probably fits well into Visual Tools section discussed in #9
Hands-on RISC-V Processor Design
This tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA). The course covers the following:
https://quicksilicon.in/course/riscv
Some exposure to using SystemVerilog for Design is recommended but not necessary
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Learn with SHAKTI
SHAKTI is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT-Madras.
This Tutorial Resource guides one to writing RISC-V assembly and C Programs and implement them on Spike, RISC-V GDB and OpenOCD tools. There are Assignments and Sample Programs to get started with.
https://shakti.org.in/learn_with_shakti/intro.html
Basic exposure to RISC-V ASM and C Programming
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Implementing a Linker from Scratch
This is an open course launched by PLCT Lab. In this course, we use Go to implement an RV64GC (RISC-V 64-bit) architecture linker from scratch, which can correctly link relatively simple C programs. By studying this course, one should be able to have a solid understanding of how the core parts of a static linker work.
This is an intermediate-level course.
LinuxFoundationX: RISC-V Toolchain and Compiler Optimization Techniques
Develop a working knowledge of the internals of compiler toolchains and compiler optimization techniques with a focus on RISC-V applications.
The course presumes the student will have familiarity with C/C++ applications, how programs are compiled to make them executable as well as the basics of computer science. Learners should also be familiar with basic git commands and know how to install various Linux packages.
Intermediate level course.
NEORV32
A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. The project is highly documented, powered by a nice community, includes software examples, demo FPGA setups and targets FPGA/RISC-V starters as well as advanced users.
https://github.com/stnolting/neorv32
If further information is required I'm happy to provide it 😉
RISC-V enthusiast and community member having +4 years of hobby and professional RISC-V experience in academia and research. The NEORV32 processor has already been incorporated into commercial products as well as several research projects (see Google scholar). The project is listed in the RISC-V architecture ID list, the RISC-V Exchange data base and also in RISC-V Landscape.
RVV intrinsics viewer
A third party documentation website for the vector extension intrinsics, currently including pretty much all intrinsics variations, and fuzzy search.
https://dzaima.github.io/intrinsics-viewer/
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Introdução à Assembly de RISC-V
It's a series of YouTube videos, in Portuguese, produced as material for the Teaching Assistant program of the CI1210 ("Projetos Digitais e Microprocessadores", free-translated to "Digital Projects and Microprocessors") classes of the Computer Science degree at the Universidade Federal do Paraná (Federal University of Paraná), Brazil. It encompasses the basic RISC-V IM architecture and uses the EGG emulator.
The series is not yet complete, the production is ongoing.
https://youtube.com/playlist?list=PLFe3Zrf4uj4vlRF21jK3vzfCuSSJ5I_uB&si=bx4eHYpPLBxAUTy8
Basic C programming and digital logic understanding is desired.
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