riscv / learn Goto Github PK

Contact Details

[email protected]

Request Details

References to beginner and intermediate level resources are broken

Resource Title

OpenSecurityTraining2 Architecture 1005: RISC-V Assembly

Resource Description

[extracted from their linkedin announcement post]
The class covers the RISC-V RV32I/RV64I base ISAs, the "C" Compressed instructions, and the "M" multiply/divide/remainder extensions.
The class also includes the CMU binary bomb lab, running in a RISC-V QEMU VM. AND as a special bonus, it includes a sneak peek at the Ghidra-for-debugging class material!

This class takes ~28 hours on average (not counting the binary bomb lab, or optional Ghidra installation & setup time.)

[this part I wrote myself]

The content is free and very hands-on, you're expected to actually run risc-v code and follow the execution with GDB, and there are multiple rounds of randomly generated assembly challenges for you to "run" and find the final result.

Resource Link

https://p.ost2.fyi/courses/course-v1:OpenSecurityTraining2+Arch1005_IntroRISCV+2024_v1/course/

Required Background (Optional)

C programming language experience is expected

Additional Details (Optional)

No response

Resource Title

Building a RISC-V CPU core - Steve Hoover

Resource Description

This free EdX course by Steve Hoover (founder of Redwood EDA) is a great way for a beginner to get started with digital logic design and basic RISC-V microarchitecture design with the help of modern, freely available open source tools such as the Makerchip IDE all from the convenience of your browser. This course provides a hands on experience with the RISC-V ISA and modern open-source logic design tools which utilize the features of a powerful and emerging HDL, Transaction-Level Verilog, designed by Redwood EDA.

Resource Link

Edx Course Link

Required Background (Optional)

No prerequisites required, this course covers all the basics from scratch, although an introductory knowledge on what RISC-V is would be helpful.

Additional Details (Optional)

This course is a beginner level course, it's best suited for enthusiasts with minimal exposure to Digital Design and Computer Architecture.

Contact Details

Ajith P V, [email protected]

Request Details

It would be better to add one more section for some of the best visual tools that helps to understand the RISC-V in a better way.
These tools can be used during the beginner or intermediate tutorials to get the visualization of the RISC-V ISA.

Example:

1. emulsiV:
   emulsiV is a visual simulator for a simple RISC processor called Virgule.
   Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, “minimal” means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program.

2. RISC-V Instruction Encoder/Decoder:
   This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other.

Resource Title

Tutorial: RISC-V Vector Extension Demystified [Andes]

Resource Description

A very in-depth, three hour long video introduction to the RISC-V Vector extension.

Resource Link

https://youtu.be/oTaOd8qr53U

Required Background (Optional)

No response

Additional Details (Optional)

No response

Resource Title

Computer Architecture- A Quantitative Approach-6th Edition, by David A. Patterson and John L. Hennessey

Resource Description

Covers advanced computer architecture concepts pertaining to high performance computing principles and domain specific architectures along with examples and exercises pertaining to the RISC-V ISA-(6th Edition onwards). This is a step-up from the first book,(Hardware-Software Interface), with advanced concepts like Instruction , Data and Thread Level Parallelism along with introduction to Vector, SIMD and GPU architectures.
It also continues the tradition of using real-world examples to demonstrate the concepts, by introducing memory organizations and architectures of ARM Cortex A8, Intel Core i7, Nvidia GTX-280 GPUs and so on.

Resource Link

Amazon Book Link

Required Background (Optional)

Prerequisites : Digital Design, Basic Computer Architecture Concepts, and introductory knowledge on the RISC-V ISA.
The reader is recommended to finish the Computer Organization and Design -Hardware Software Interface-RISC-V edition first, before moving forward with this book.

Additional Details (Optional)

This book is generally preferred for Master Students, so I would suggest to keep this resource in the Advanced resource section after the Intermediate stage. This book could still be included in the intermediate section, but the Hardware Software Interface is a necessary prerequisite to have a clear understanding of the concepts.

Resource Title

Step-by-step RISC-V C Compiler development

Resource Description

This MOOC is an online educational course that teaches how to develop a simple RISCV C language compiler from scratch step by step.

The video of this course is at: https://www.bilibili.com/video/BV1gY4y1E7Ue
The sample code of this course is at: https://github.com/sunshaoce/rvcc
The teaching resources of this course is at: https://github.com/sunshaoce/rvcc-course

Resource Link

https://www.bilibili.com/video/BV1gY4y1E7Ue

Required Background (Optional)

1. Be relatively proficient in C language programming.
2. Master basic data structures, such as arrays and linked lists, etc.

Videos, slides, sample codes and comments are all in Chinese.

Additional Details (Optional)

For more information please contact MOOC author: Shao-Ce SUN [email protected]

github id: https://github.com/sunshaoce

Resource Title

Step by step development of a RISC-V operating system

Resource Description

This MOOC is an online education course that introduces the relevant knowledge of riscv and teaches how to develop a simple riscv operating system from scratch step by step.

The video of this course is at: https://www.bilibili.com/video/BV1Q5411w7z5
The teaching resources and sample code of this course are at: https://github.com/plctlab/riscv-operating-system-mooc

This MOOC has been very popular since it was launched in the spring of 2021.

Resource Link

https://github.com/plctlab/riscv-operating-system-mooc

Required Background (Optional)

• Be relatively proficient in C language programming.
• Master basic data structures, such as arrays and linked lists, etc.
• Understand Linux and common command operations.

Videos and slides are in Chinese, sample codes and comments are in English.

Additional Details (Optional)

For more information please contact MOOC author: Chen Wang [email protected]
github id: https://github.com/unicornx

Resource Title

RVfpga 3.0: Understanding Computer Architecture

Resource Description

The RVfpga Course in Computer Architecture provides hands-on understanding of a commercial RISC-V processor, RISC-V SoC, and the RISC-V ecosystem. Specifically, the RVfpga v3.0 course shows how to target a VeeR EL2 and a VeeR EH1 based system-on-chip (SoC) to 3 different FPGA boards: the Digilent Basys 3 board ($124 academic price), the Real Digital Boolean board ($74 academic price), and the Digilent Nexys A7 board ($262 academic price). The course can also be completed only in simulation; for that purpose, several simulation tools are provided which enable the user to simulate the system at different levels: from a Boolean/Nexys A7/Basys 3 virtual board down to the VeeR EH1/EL2 pipeline.

Resource Link

https://university.imgtec.com/rvfpga-el2-v3-0-english-downloads-page/

Required Background (Optional)

Expected Prior Knowledge:
– Digital design
– High-level programming (preferably C)
– Instruction set architecture / assembly programming
– Microarchitecture
– Memory systems

All this material is covered in Digital Design and Computer Architecture: RISC-V Edition, Harris & Harris, Elsevier 2021.

Additional Details (Optional)

Please contact with Daniel Chaver at [email protected] for any questions or comments.

Resource Title

CREATOR

Resource Description

CREATOR is a didactic simulator that allows the development, simulation, and debugging of RISC-V (RV32IMFD) assembly programs intuitively and interactively. It is a web application, so it can be used on any type of device (desktop, tablet, smartphone, etc.) without installing additional software, only a modern web browser (Google Chrome, Mozilla Firefox, Apple Safari, etc.) is required.

For more information: https://creatorsim.github.io/

Resource Link

https://creatorsim.github.io/creator/

Required Background (Optional)

• Programming basics (loops, conditionals, functions, etc.)

Additional Details (Optional)

We have seen issue #9 , if a new category of visual tools is added, CREATOR we believe fits in this category. Otherwise, we believe that it fits in the section "Intermediate-Level resources"

Resource Title

Tiny-asm

Resource Description

Tiny-asm is a standard C RISCV assembler derived from GNU gas. It is very small and easy to compile and install, since it consists of only 2 files: asm.c and asm.h. It is in
https://github.com/jacob-navia/tiny-asm.git
This repository includes the documentation.

Resource Link

https://github.com/jacob-navia/tiny-asm.git

Required Background (Optional)

If you want to tinker with the assembler you have to know the C language.
The documentation is in English
Yoiu can compile the assembler in any machine that supports standard C.

Additional Details (Optional)

For more information, donations, whatever:
[email protected]

Resource Title

QtRvSim - RISC-V CPU Simulator with Cache and Pipeline Visualization

Resource Description

QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. The project page https://github.com/cvut/qtrvsim/ provides links to GNU/Linux, Mac OS and Windows native binaries. Online version and related courses materials are available at https://comparch.edu.cvut.cz/ . It provides enough subsystems to run, port or implement a simple (no memory protection or paging; M-mode only) operating system with preemptive multitasking.

Resource Link

https://github.com/cvut/qtrvsim

Required Background (Optional)

Basic or intermediate, ideal companion tool to Computer Organization and Design RISC-V edition: The Hardware Software Interface textbook.

Additional Details (Optional)

Probably fits well into Visual Tools section discussed in #9

Resource Title

Hands-on RISC-V Processor Design

Resource Description

This tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA). The course covers the following:

• Fundamental concepts of computer architecture and processor design
• Practical exposure to the unprivileged RISC-V Instruction Set Architecture (ISA)
• Learn to design a single-cycle RV32I compliant processor from scratch in SystemVerilog
• Create RISC-V assembly programs and execute them on the designed processor

Resource Link

https://quicksilicon.in/course/riscv

Required Background (Optional)

Some exposure to using SystemVerilog for Design is recommended but not necessary

Additional Details (Optional)

No response

Resource Title

Learn with SHAKTI

Resource Description

SHAKTI is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT-Madras.
This Tutorial Resource guides one to writing RISC-V assembly and C Programs and implement them on Spike, RISC-V GDB and OpenOCD tools. There are Assignments and Sample Programs to get started with.

Resource Link

https://shakti.org.in/learn_with_shakti/intro.html

Required Background (Optional)

Basic exposure to RISC-V ASM and C Programming

Additional Details (Optional)

No response

Resource Title

Implementing a Linker from Scratch

Resource Description

This is an open course launched by PLCT Lab. In this course, we use Go to implement an RV64GC (RISC-V 64-bit) architecture linker from scratch, which can correctly link relatively simple C programs. By studying this course, one should be able to have a solid understanding of how the core parts of a static linker work.

Resource Link

https://github.com/ksco/rvld

Required Background (Optional)

1. Familiar with the Go programming language.
2. Have a basic understanding of the RISC-V instruction set.
3. Have a basic understanding of the compilation process.
4. The code repository is English-friendly, course videos and materials are only available in Chinese.

Additional Details (Optional)

This is an intermediate-level course.

Resource Title

LinuxFoundationX: RISC-V Toolchain and Compiler Optimization Techniques

Resource Description

Develop a working knowledge of the internals of compiler toolchains and compiler optimization techniques with a focus on RISC-V applications.

Resource Link

https://www.edx.org/learn/computer-programming/the-linux-foundation-risc-v-toolchain-and-compiler-optimization-techniques?index=product&queryID=e9776f6d9ec571d2057b52f271c08fc2&position=7&results_level=second-level-results&term=riscv&objectID=course-6bb0f3e7-ecdd-425b-b573-d0fd642f6e50&campaign=RISC-V+Toolchain+and+Compiler+Optimization+Techniques&source=edX&product_category=course&placement_url=https%3A%2F%2Fwww.edx.org%2Fsearch

Required Background (Optional)

The course presumes the student will have familiarity with C/C++ applications, how programs are compiled to make them executable as well as the basics of computer science. Learners should also be familiar with basic git commands and know how to install various Linux packages.

Additional Details (Optional)

Intermediate level course.

Resource Title

NEORV32

Resource Description

A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. The project is highly documented, powered by a nice community, includes software examples, demo FPGA setups and targets FPGA/RISC-V starters as well as advanced users.

Resource Link

https://github.com/stnolting/neorv32

Required Background (Optional)

If further information is required I'm happy to provide it 😉

Additional Details (Optional)

RISC-V enthusiast and community member having +4 years of hobby and professional RISC-V experience in academia and research. The NEORV32 processor has already been incorporated into commercial products as well as several research projects (see Google scholar). The project is listed in the RISC-V architecture ID list, the RISC-V Exchange data base and also in RISC-V Landscape.

Resource Title

RVV intrinsics viewer

Resource Description

A third party documentation website for the vector extension intrinsics, currently including pretty much all intrinsics variations, and fuzzy search.

Resource Link

https://dzaima.github.io/intrinsics-viewer/

Required Background (Optional)

No response

Additional Details (Optional)

No response

Resource Title

Introdução à Assembly de RISC-V

Resource Description

It's a series of YouTube videos, in Portuguese, produced as material for the Teaching Assistant program of the CI1210 ("Projetos Digitais e Microprocessadores", free-translated to "Digital Projects and Microprocessors") classes of the Computer Science degree at the Universidade Federal do Paraná (Federal University of Paraná), Brazil. It encompasses the basic RISC-V IM architecture and uses the EGG emulator.

The series is not yet complete, the production is ongoing.

Resource Link

https://youtube.com/playlist?list=PLFe3Zrf4uj4vlRF21jK3vzfCuSSJ5I_uB&si=bx4eHYpPLBxAUTy8

Required Background (Optional)

Basic C programming and digital logic understanding is desired.

Additional Details (Optional)

No response