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A FPGA friendly 32 bit RISC-V CPU implementation

License: MIT License

Scala 26.91% C++ 4.69% Makefile 0.87% Assembly 62.02% Verilog 0.26% Python 0.13% Shell 0.08% C 3.82% Tcl 1.21% Java 0.01%
riscv soc cpu spinalhdl vhdl verilog fpga softcore

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raj347 bcfanny plex1 drichmond gitter-badger kaofishy wallbraker kuanwoo halferty jackboranzhao hevs-isi jens-na tomverbeure xobs yinxx mcmasterg mithro burt0927 abhisit eine curliph mgielda victortagayun yokeung rogerxujiang wiltonlazary antmicro michaeljclark ckj119940887 microbuilder danickpan daverichmond rowhit cutephoton wifasoi circuit-killer lawrie younghogong amirzainol shirishbahirat kamejoko80 mani-sadhasivam roman3017 lanjunjie250 kandeshvari maswx tianyouw louieatwi bedros rakeshm75 wieker hxlled 2php stlcours gentel86 ocakgun ruishihan rpls octaplexsys rpicas marekpikula alex-hardware shufps nq-quan ckdur wya2017 simudai reprapthailand sebastien-riou jnsquire bellaz89 puskyer japm48 observersputnik nickolayternovoy eedesignhouse moneytech genesys2 bethewind gwsu andy89926 aerotic hex55 thuchoang90 geminiz yokoyama-flogics doitdodo strong-ting wuxx xujwoo dbhi mapper alexzhang007 awfeequdng longervisionuk liangkangnan connorwk tingaxio xushoucai iceshy

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