The install docs (https://github.com/tinyvision-ai-inc/UPduino-v3.0/blob/master/docs/source/getting_started/tool_installation.rst) mention that a fork of apio may be required. I thought I would check just to see and the pip-version of apio seems to include UPDuino versions up to 3.1:

tim@lindawg ~/riscv $ python3
python3            python3.10         python3.10-config  python3-config     
tim@lindawg ~/riscv $ python3 -m venv venv
tim@lindawg ~/riscv $ . venv/bin/activate
(venv) tim@lindawg ~/riscv $ pip3 install apio
...
(venv) tim@lindawg ~/riscv $ apio boards -l | grep upd
upduino          iCE40-UP5K-SG48                ice40    up           5k    sg48      
upduino2         iCE40-UP5K-SG48                ice40    up           5k    sg48      
upduino21        iCE40-UP5K-SG48                ice40    up           5k    sg48      
upduino3         iCE40-UP5K-SG48                ice40    up           5k    sg48      
upduino31        iCE40-UP5K-SG48                ice40    up           5k    sg48      
(venv) tim@lindawg ~/riscv $ 

There is a general confusion of what header side is left and right. For example, if we take pin gpio_23.

In the pcf files it's listed as 'left'

# Normal GPIO pins, left side
set_io -nowarn gpio_23 23

In the schematic it's on the right header symbol

In the Kicad 3D rendering its on the right header.

Please fix it to have consistent and intuitive orientation. This can be done with spinning a new PCB by

1. In the schematic swap the positions of the two header symbols.

2. In the headers footprint, rotate the 3D model of the pins to be on the other side of the PCB.

This will make everything consistent for this 'canonical' orientation (view from top):

I am getting a build error running make in the RTL/blink_led/ directory:

> make
yosys -q -p "synth_ice40 -json rgb_blink.json" rgb_blink.v
ERROR: Module rgb_blink contains processes, which are not supported by JSON backend (run `proc` first).
make: *** [rgb_blink.json] Error 1

I am on an Intel Mac running Big Sur (11.6.5) with yosys installed via Homebrew:

> where yosys
/usr/local/bin/yosys
> yosys --version
Yosys 0.16 (git sha1 UNKNOWN, clang 13.0.0 -fPIC -Os)

Version 0.16 is the latest version, release April 5, 2022 on their Github Page.

Are UPduino V3.0 and V3.1 compatible with this "HM01B0-UPD-EVN"? If positive, is there any documentation available on that subject?

Please update the APIO documentation at https://upduino.readthedocs.io/en/latest/getting_started/tool_installation.html .

Upduino 3.1 is now supported by the APIO release and the upcoming APIO release will also include two Updiono 3.1 examples that can be created in user space using the apio examples command.

https://github.com/FPGAwars/apio-examples/tree/master/upduino31

I suggest to also add to https://upduino.readthedocs.io/en/latest/getting_started/tool_installation.html a shot explanation on how to install APIO, instantiate the APIO blinky example and build and upload. It should not take more than a few lines of code and will provide a quick start to new Upduino users.

The v3.0 reduced the available current from the 3.3V supply as compared to the v2. Increase the current by adding a switcher to the design to limit power dissipation while giving users the ability to draw much more power from the 3.3V supply on the board. Thanks to @BAYoussef for this suggestion.

Great work! I really like the UPduino boards!

Interested in yet another RISC-V SoC for the Board? ;)

https://github.com/stnolting/neorv32

It is a full-scale rv32imc + privileged architecture RISC-V processor with SPI, I²C, PWM, GPIO, TIMER and a Watchdog. The whole SoC perfectly fits in a ice40 up5k FPGA and runs at 22MHz (tested on UPduino v2.0). The project comes with some example programs and a bootloader capable of storing/booting an executable from the on-board FPGA configuration flash.

Best regards

• Switch to KiCAD

Board layout:

• 4 layer board, solid ground plane, dedicated power layer for 3.3V and 1.2V distribution
• Any optional bridges must be done using special bridge-type footprint instead of resistors to make modification easy
  All passives to be no smaller than 0603 footprint
• Fix silkscreen so its easy to read, add Pb Free, WEEE symbol, "Made in USA"
• Move Micro USB connector inboard a little bit to allow clean depanelization

Power

• Dedicated power and ground planes
• Minimum of 10uF bulk capacitance on all power rails: USB, 3.3V, 1.2V
• Dedicated decoupling capacitance on each FPGA pin placed close the FPGA pin
• Power decoupling per FTDI recommendations (using ferrite beads)
• Change LDO's to be smaller parts, capable of 200mA max output

Oscillator:

• 12MHz crystal oscillator to replace the resonator for stability
• Solder bridge option to connect the 12MHz oscillator to the FPGA

Flash

• qSPI option using the currently unused pin 10, 20 (layout permitting)
• DTR capable flash to support even higher throughput

Programming:

• Connect DONE signal to the FTDI
• FPGA CRAM programming capability

LED:

• Smaller 3 color LED?
• Bring out the 3 color LED pins to alternate (DNI) LED footprints to allow these to be used for other applications such as IR LED's etc.

Sample code:

• Ship with RISCV port instead of very simple blinky

Optional

• Support for the tinyFPGA bootloader by DNI'ing the FTDI for a low-cost option

The SB_PLL40_PAD primitive requires clock_in to come from pin 35 and cannot be instantiated with the external clock connected to pin 20. Please consider moving the external clk to pin 35 in next version.

$ ./icepll -p -m -i 12 -o 30

/**
 * PLL configuration
 *
 * This Verilog module was generated automatically
 * using the icepll tool from the IceStorm project.
 * Use at your own risk.
 *
 * Given input frequency:        12.000 MHz
 * Requested output frequency:   30.000 MHz
 * Achieved output frequency:    30.000 MHz
 */

module pll(
	input  clock_in,
	output clock_out,
	output locked
	);

SB_PLL40_PAD #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),		// DIVR =  0
		.DIVF(7'b1001111),	// DIVF = 79
		.DIVQ(3'b101),		// DIVQ =  5
		.FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.PACKAGEPIN(clock_in),
		.PLLOUTCORE(clock_out)
		);

endmodule

The current UPduino 3.0 design doesnt allow the UART to be used if the FPGA is accessing the Flash.
Designs like the RISCV use the Flash but also need access to the UART at the same time.

• Add UART (non flow controlled) access to the UPduino independent of the flash
• Keep cost the same
• Minimize use of extra pins, ideally keep this pin compatible with the UPduino 2.x

Missing UPduino3.0 lib file in kicad board folder

Looking at the schematic vs the actual board, there appears to be an inconsistency regarding the location of the 12MHz output. From the USB connector on downwards, the pins on the board are marked as "10", "12M", "GND", "12", etc. However, according to the schematic it's "10", "GND", "12M", "12" (that is: 12M and GND are swapped).

Which is the correct one?

The three LEDs don't have current limiting resistors. When a LED is on, do the FPGA outputs that drive them operate within spec?

Hi all,
i purchased an upduino v3 card through tindie on june 26th. I think there is a little problem with the silkscreen of PCB. Indeed there seems to be a reversal between pin 7 and pin 8 of the left J3 connector. Pin J3-7 marked CLK_12M_EXT is equipotential with the other GNDs and pin J3-8 marked GND generates a square wave of 12MHz frequency.

I'm able to build and verify the blinky_led example with apio, but am unable to upload. I see the below error:

C:\Users\davec\Documents\apio\UPduino-v3.0\RTL\blink_led>apio upload
(DEBUG) Profile path: C:\Users\davec\.apio\profile.json
(DEBUG) Home_dir: C:\Users\davec\.apio
(DEBUG) Profile path: C:\Users\davec\.apio\profile.json
(DEBUG) Home_dir: C:\Users\davec\.apio
(DEBUG) Run Command: lsusb
(DEBUG) System_base_dir: C:\Users\davec\.apio\packages\tools-oss-cad-suite
(DEBUG) System bin dir: C:\Users\davec\.apio\packages\tools-oss-cad-suite\bin
(DEBUG) Executable file: C:\Users\davec\.apio\packages\tools-oss-cad-suite\bin\lsusb.exe
(DEBUG) Profile path: C:\Users\davec\.apio\profile.json
(DEBUG) Home_dir: C:\Users\davec\.apio
(DEBUG) Run Command: lsftdi
(DEBUG) System_base_dir: C:\Users\davec\.apio\packages\tools-oss-cad-suite
(DEBUG) System bin dir: C:\Users\davec\.apio\packages\tools-oss-cad-suite\bin
(DEBUG) Executable file: C:\Users\davec\.apio\packages\tools-oss-cad-suite\bin\lsftdi.exe
Error: board upduino3 not connected

It seems the board is connected to my machine according to apio system --lsftdi:

C:\Users\davec\Documents\apio\UPduino-v3.0\RTL\blink_led>apio system --lsftdi
(DEBUG) Profile path: C:\Users\davec\.apio\profile.json
(DEBUG) Home_dir: C:\Users\davec\.apio
(DEBUG) Run Command: lsftdi
(DEBUG) System_base_dir: C:\Users\davec\.apio\packages\tools-oss-cad-suite
(DEBUG) System bin dir: C:\Users\davec\.apio\packages\tools-oss-cad-suite\bin
(DEBUG) Executable file: C:\Users\davec\.apio\packages\tools-oss-cad-suite\bin\lsftdi.exe
Number of FTDI devices found: 1
Checking device: 0
Manufacturer: tinyVision.ai, Description: UPduino v3.1

I followed Shawn Hymel's FPGA tutorials on youtube (on Part 2) to get to this point. I've used Zadig to make sure libusbK is the selected driver for the UPduino v3.1 board seen by Zadig.

Have others run into this error?

I was trying an to use the FPGA as a spi slave for booting from an external processor to load a configuration directly into the FPGA. I realized then when I go through the boot sequence and pull SS low for the FPGA, it also pulls SS low on the SPI EEPROM. I was hoping I could use the R11/12/13/27 jumpers, but that won't help because the flash pins are on the 3 & 4 of the board connector. If the FPGA pins were on the board connectors ie FPGA_SI (needed) and FPGA_SO (not realy needed) instead of FLASH_MOSI and FLASH_MSIO, that would solve my issue or other jumpers to assign the board connectors 3&4 between FLASH and FPGA.

Thanks for considering this for 3.x or 4.0.
James

This needs fixing on the gerbers

I downloaded this repository and ran apio init --board upduino3 then apio verify

It would be great to have support (both a platform file and a target file) in litex-boards for v3.1.

I did find these for v1: https://github.com/timvideos/litex-buildenv/blob/master/targets/upduino_v1/base.py (target file), https://github.com/timvideos/litex-buildenv/blob/master/platforms/upduino_v1.py (platform file).

Probably some of the pinout in the platform file would need updating, and it might need some massaging to move it to litex-boards.

Noticed that the schematic did not match the silkscreen on LHS (J3) pins 7 and 8. Quick test shows that the issue is with the silkscreen.

Pin 30 is not shown explicitly but is connected.
Pin 30 should be shown as a separate pin instead of an overlapping connection.

Having the OSC jumper connected by default will improve the out of the box experience.

Please have it connected by default in the next version, e.g. using a solder jumper footprint that can be populated with a zero ohms 0402 resistor, or even just a standard 0402 resistor footprint.