Topic: physical-design Goto Github
Some thing interesting about physical-design
Some thing interesting about physical-design
physical-design,Physical Design Flow from RTL to GDS using Opensource tools.
User: akilm
Home Page: https://www.vlsisystemdesign.com/
physical-design,Create fast and efficient standard cell based adders, multipliers and multiply-adders.
User: antonblanchard
physical-design,This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI System Design Corporation. This workshop helped me gain hands-on experience with tools that are used in the physical design flow.
User: bidyendughoshal
Home Page: https://www.vlsisystemdesign.com/
physical-design,MNT Bench - An MNT tool for Benchmarking FCN circuits
Organization: cda-tum
Home Page: https://www.cda.cit.tum.de/mntbench/
physical-design,Design, layout, and simulation files of the paper "Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface" by M. Walter, J. Croshaw, S. S. H. Ng, K. Walus, R. Wolkow, and R. Wille in DATE 2024.
Organization: cda-tum
physical-design,RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Organization: cuhk-eda
physical-design,Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
Organization: cuhk-eda
physical-design,Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
User: daikon-sun
physical-design,Routing Visualization for Physical Design
User: daikon-sun
physical-design,Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Organization: eclufsc
physical-design,generic NetList data structure for VLSI
Organization: eda-rs
physical-design,RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
User: felipefferreira
physical-design,Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
User: gabrielganzer
physical-design,Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
User: gabrielganzer
physical-design,Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
User: jordanpui
physical-design,Physical Design (2020 Spring)
User: linkingmon
physical-design,Contains the all the assignments of CMOS ASIC Design Lab
User: manjunathkalmath
physical-design,PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
User: mostafa-elgendy22
physical-design,Source files for the labs of the Microelectronic Systems course
User: mrcuve0
physical-design,VSDMemSOC Implementation flow:: RTL2GDSII
User: pa1mantri
physical-design,Final project at San Jose State University
User: puravbhatt
physical-design,Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
User: saathi7
physical-design,EDA physical synthesis optimization kit
Organization: scale-lab
Home Page: https://woset-workshop.github.io/PDFs/2020/a09.pdf
physical-design,This repository is my entry into scripting using TCL and an attempt to understand it's nuances in physical design flow in VLSI
User: shobhit-mittra
physical-design,This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.
User: shobhit-mittra
physical-design,Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo
User: siddharth13s
physical-design,GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
User: vardhansuroshi
physical-design,Testcase generator and visualizer and verification for your 2019 CAD Contest Problem E
User: voidism
physical-design,Physical Design for nanometer ICs @NTUEE
User: wayne1204
physical-design,N25K200 2023 NCKU-PHYSICAL DESIGN for NANOMETER IC's Projects
User: xkllkx
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