module PWMTL_pwm :
input clock : Clock
input reset : UInt<1>
output io : {interrupts : {}, flip in : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<14>, mask : UInt<4>, data : UInt<32>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<14>, mask : UInt<4>, data : UInt<32>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<14>, data : UInt<32>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, addr_lo : UInt<2>, data : UInt<32>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<1>}}}}, pwmout : UInt<1>}
clock is invalid
reset is invalid
io is invalid
reg period : UInt<32>, clock @[PWM.scala 49:19]
reg duty : UInt<32>, clock @[PWM.scala 51:17]
reg enable : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[PWM.scala 53:23]
inst base of PWMBase @[PWM.scala 55:20]
// comments : in lines above , PWMbase shall be instanced. however, at the end , PWMBase module is totally removed, I don't know why , I just follow the instruction steps make PROJECT=example Confing= PWMConfig, nothing else. The result is PWMBase disappear
Any one who have same situations that could share ?
io.pwmout <= base.io.pwmout @[PWM.scala 56:13]