Processor not writing to data memory about vexriscv

[Dolu1990]

Hi,

Would it be possible to have the vcd with all the signals ? (including the CPU signals)

Thanks :)

[yannickl96]

You mean the internal processor signals?

[Dolu1990]

Yes ^^

[Dolu1990]

Hooo are you debugging directly on the physical target ?

[yannickl96]

Yes, sir ^^. In theory, the processor should work fine (at least according to the regression tests). However, on the Xilinx PYNQ-Z1 there are some problems.

[yannickl96]

@Dolu1990 I have to add the signals post-synthesis which results in about 1200 signals (and my PYNQ doesn't have nearly enough BRAM to save them all). Are there any signals which are more helpful to you than others?

[dronox]

Maybe you can check formal equivalence of netlist and RTL design first to make sure there is no issue introduced due to synthesis? Synopsys Formality or similar tools might help, here!

[yannickl96]

Thank you for the hint! I will give it a try.

[Dolu1990]

@yannickl96 Sorry had lost the track of this issue.

So, the thing is you realy need to do a simulation to sort this kind of things out, especialy if you have a whole system/third party stuff in the project. Debuging it the half blind is realy a paine full process :)

About synthesis issues, i have to say that this kind of issue already happend to me on Zynq. That's quite a paine in the ass if that's the case there :/

[yannickl96]

Well, it would not be the first time that Vivado would do something unfortunate. -.-^^

[yannickl96]

@Dolu1990 Did your synthesis issue on your Zynq by any chance emerge due to an error in the memory map?

[Dolu1990]

Yes, exactly, it was the issue. Bad memory synthesis, and it was somehow quite random.