stevehoover / warp-v Goto Github PK
View Code? Open in Web Editor NEWWARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
Home Page: https://warp-v.org
License: BSD 3-Clause "New" or "Revised" License
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
Home Page: https://warp-v.org
License: BSD 3-Clause "New" or "Revised" License
\m4_TLV_version 1d: tl-x.org
\SV
`include "./sv_url_inc/picorv32_pcpi_div.sv" // From: "https://raw.githubusercontent.com/stevehoover/warp-v_includes/master/divmul/picorv32_pcpi_div.sv"
m4_sv_include_url(['https://raw.githubusercontent.com/stevehoover/warp-v_includes/master/divmul/picorv32_pcpi_div.sv'])
The 'Download Verilog' and "Open in Makerchip IDE" buttons don't work.
Any pipeline staging modification can cause an error message about BUBBLEs and a simulation segfault in Makerchip. There is an ordering requirement on redirects, similar to the ordering requirement on pipeline stages. This is affected by the EXTRA_*_BUBBLEs. We could:
Let's do the 4th option. So use all 0 defaults, and add a note "EXTRA_*_BUBBLEs (0 or 1). Set to 1 to add a cycle to replay conditions to relax circuit timing. (Not all configurations are valid.)"
In the downloaded Verilog file the ``include "sp_default.vh"` line is still present.
LD_RETURN_ALIGN is different. It must be >= (EXECUTE_STAGE - NEXT_PC_STAGE) (I think).
Quick start link does not yield a working makerchip page:
WARP-V is easiest to explore in Makerchip. You can:
The diagram tab will error out.
Instruction memory inside Warp-V when compiled by sandpiper , produced system verilog or verilog will give an error while synthesis due to incorrect format of array declaration due to line 1448.
BUBBLE
parameters, "CPU cores". STAGE
parameters may be negative (or not; either convention is fine).STAGE
parameters must be monotonically non-decreasing.m4_defines
to m4_ifndef
, which means, these will only define defaults, and not override provided values. I will also remove defaults below for BRANCH_PRED
and DATA_MEM_WORDS
.) Selection on pipeline depth should adjust the stage parameters. Adjusting stage parameters should uncheck the "Pipeline Depth" choice (so none-selected). You could use STANDARD_CONFIG
when a "Pipeline Depth" is selected and detailed STAGE
values otherwise.Pipeline defaults:
m4_case(M4_STANDARD_CONFIG,
['1-stage'], ['
// No pipeline
m4_defines(
(M4_NEXT_PC_STAGE, 0),
(M4_FETCH_STAGE, 0),
(M4_DECODE_STAGE, 0),
(M4_BRANCH_PRED_STAGE, 0),
(M4_REG_RD_STAGE, 0),
(M4_EXECUTE_STAGE, 0),
(M4_RESULT_STAGE, 0),
(M4_REG_WR_STAGE, 0),
(M4_MEM_WR_STAGE, 0),
(M4_LD_RETURN_ALIGN, 1))
m4_default(['M4_BRANCH_PRED'], ['fallthrough'])
m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
'],
['2-stage'], ['
// 2-stage pipeline.
m4_defines(
(M4_NEXT_PC_STAGE, 0),
(M4_FETCH_STAGE, 0),
(M4_DECODE_STAGE, 0),
(M4_BRANCH_PRED_STAGE, 0),
(M4_REG_RD_STAGE, 0),
(M4_EXECUTE_STAGE, 1),
(M4_RESULT_STAGE, 1),
(M4_REG_WR_STAGE, 1),
(M4_MEM_WR_STAGE, 1),
(M4_LD_RETURN_ALIGN, 2))
m4_define(['M4_BRANCH_PRED'], ['two_bit'])
m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
'],
['4-stage'], ['
// A reasonable 4-stage pipeline.
m4_defines(
(M4_NEXT_PC_STAGE, 0),
(M4_FETCH_STAGE, 0),
(M4_DECODE_STAGE, 1),
(M4_BRANCH_PRED_STAGE, 1),
(M4_REG_RD_STAGE, 1),
(M4_EXECUTE_STAGE, 2),
(M4_RESULT_STAGE, 2),
(M4_REG_WR_STAGE, 3),
(M4_MEM_WR_STAGE, 3),
(M4_EXTRA_REPLAY_BUBBLE, 1),
(M4_LD_RETURN_ALIGN, 4))
m4_define(['M4_BRANCH_PRED'], ['two_bit'])
m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
'],
['6-stage'], ['
// Deep pipeline
m4_defines(
(M4_NEXT_PC_STAGE, 1),
(M4_FETCH_STAGE, 1),
(M4_DECODE_STAGE, 3),
(M4_BRANCH_PRED_STAGE, 4),
(M4_REG_RD_STAGE, 4),
(M4_EXECUTE_STAGE, 5),
(M4_RESULT_STAGE, 5),
(M4_REG_WR_STAGE, 6),
(M4_MEM_WR_STAGE, 7),
(M4_EXTRA_REPLAY_BUBBLE, 1),
(M4_LD_RETURN_ALIGN, 7))
m4_default(['M4_BRANCH_PRED'], ['two_bit'])
m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
']
)
SandPiper supports a number of --fmt*
options that control the formatting of the generated Verilog. It would be nice to provide access in the configurator to these options. (This would, of course, be useful from Makerchip as well.)
Configurator tweaks:
A declarative, efficient, and flexible JavaScript library for building user interfaces.
๐ Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. ๐๐๐
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google โค๏ธ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.