• "Get your code" buttons can be all in a row.
• Resize configuration image to scale it up ~30% and crop the right side.
• Whitespace is missing from TLV code view.
• E/M extensions should be enabled by default to match WARP-V defaults.
• Opening Verilog in Makerchip will require a few code hacks:
  • A header must be added:

    \m4_TLV_version 1d: tl-x.org
    \SV
    

  • Include statements must be modified:

    `include "./sv_url_inc/picorv32_pcpi_div.sv"  // From: "https://raw.githubusercontent.com/stevehoover/warp-v_includes/master/divmul/picorv32_pcpi_div.sv"
    

    Must become:

    m4_sv_include_url(['https://raw.githubusercontent.com/stevehoover/warp-v_includes/master/divmul/picorv32_pcpi_div.sv'])
    

• The config pane size and the size of its tabs doesn't quite scale properly with the window width.

• The 'Download Verilog' and "Open in Makerchip IDE" buttons don't work.

• Any pipeline staging modification can cause an error message about BUBBLEs and a simulation segfault in Makerchip. There is an ordering requirement on redirects, similar to the ordering requirement on pipeline stages. This is affected by the EXTRA_*_BUBBLEs. We could:

  • enhance WARP-V to eliminate this constraint
  • add some complexity to the configurator
  • remove the options
  • change the defaults and add some warning text in the configurator

  Let's do the 4th option. So use all 0 defaults, and add a note "EXTRA_*_BUBBLEs (0 or 1). Set to 1 to add a cycle to replay conditions to relax circuit timing. (Not all configurations are valid.)"

• In the downloaded Verilog file the ``include "sp_default.vh"` line is still present.

• LD_RETURN_ALIGN is different. It must be >= (EXECUTE_STAGE - NEXT_PC_STAGE) (I think).

Quick start link does not yield a working makerchip page:

Quick Links

Explore WARP-V

WARP-V is easiest to explore in Makerchip. You can:

• open the entire WARP-V model as a single file

The diagram tab will error out.

https://github.com/github/linguist/blob/master/CONTRIBUTING.md#adding-a-language
https://docs.github.com/en/github/creating-cloning-and-archiving-repositories/about-repository-languages

Instruction memory inside Warp-V when compiled by sandpiper , produced system verilog or verilog will give an error while synthesis due to incorrect format of array declaration due to line 1448.

• Add ellipses (...) between two core images.
• Parameters should not be allowed to go negative. This includes BUBBLE parameters, "CPU cores". STAGE parameters may be negative (or not; either convention is fine).
• STAGE parameters must be monotonically non-decreasing.
• "Branch Prediction" description is wrong and can be removed.
• For "Code":
  • Let's have "Code" be the last tab.
  • "Formatting" => "Verilog/SystemVerilog Formatting"
  • Add a first option "Verilog (vs. SystemVerilog)". When selected add "-p verilog".
  • For "--bestsv" description, use "Optimize SystemVerilog code for readability (versus preserving line association with TL-Verilog source)."
• The default pipeline selection defines default values for pipeline stages.
  • I don't like to redundantly have the default values in JS, but that's probably the easiest way to move forward. Defaults are below. (I will be changing m4_defines to m4_ifndef, which means, these will only define defaults, and not override provided values. I will also remove defaults below for BRANCH_PRED and DATA_MEM_WORDS.) Selection on pipeline depth should adjust the stage parameters. Adjusting stage parameters should uncheck the "Pipeline Depth" choice (so none-selected). You could use STANDARD_CONFIG when a "Pipeline Depth" is selected and detailed STAGE values otherwise.
  • Add a note to "Pipeline Depth:" => "Pipeline Depth (updates detailed parameters under "Pipeline"):"

Pipeline defaults:

   m4_case(M4_STANDARD_CONFIG,
      ['1-stage'], ['
         // No pipeline
         m4_defines(
            (M4_NEXT_PC_STAGE, 0),
            (M4_FETCH_STAGE, 0),
            (M4_DECODE_STAGE, 0),
            (M4_BRANCH_PRED_STAGE, 0),
            (M4_REG_RD_STAGE, 0),
            (M4_EXECUTE_STAGE, 0),
            (M4_RESULT_STAGE, 0),
            (M4_REG_WR_STAGE, 0),
            (M4_MEM_WR_STAGE, 0),
            (M4_LD_RETURN_ALIGN, 1))
         m4_default(['M4_BRANCH_PRED'], ['fallthrough'])
         m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
      '],
      ['2-stage'], ['
         // 2-stage pipeline.
         m4_defines(
            (M4_NEXT_PC_STAGE, 0),
            (M4_FETCH_STAGE, 0),
            (M4_DECODE_STAGE, 0),
            (M4_BRANCH_PRED_STAGE, 0),
            (M4_REG_RD_STAGE, 0),
            (M4_EXECUTE_STAGE, 1),
            (M4_RESULT_STAGE, 1),
            (M4_REG_WR_STAGE, 1),
            (M4_MEM_WR_STAGE, 1),
            (M4_LD_RETURN_ALIGN, 2))
         m4_define(['M4_BRANCH_PRED'], ['two_bit'])
         m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
      '],
      ['4-stage'], ['
         // A reasonable 4-stage pipeline.
         m4_defines(
            (M4_NEXT_PC_STAGE, 0),
            (M4_FETCH_STAGE, 0),
            (M4_DECODE_STAGE, 1),
            (M4_BRANCH_PRED_STAGE, 1),
            (M4_REG_RD_STAGE, 1),
            (M4_EXECUTE_STAGE, 2),
            (M4_RESULT_STAGE, 2),
            (M4_REG_WR_STAGE, 3),
            (M4_MEM_WR_STAGE, 3),
            (M4_EXTRA_REPLAY_BUBBLE, 1),
            (M4_LD_RETURN_ALIGN, 4))
         m4_define(['M4_BRANCH_PRED'], ['two_bit'])
         m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
      '],
      ['6-stage'], ['
         // Deep pipeline
         m4_defines(
            (M4_NEXT_PC_STAGE, 1),
            (M4_FETCH_STAGE, 1),
            (M4_DECODE_STAGE, 3),
            (M4_BRANCH_PRED_STAGE, 4),
            (M4_REG_RD_STAGE, 4),
            (M4_EXECUTE_STAGE, 5),
            (M4_RESULT_STAGE, 5),
            (M4_REG_WR_STAGE, 6),
            (M4_MEM_WR_STAGE, 7),
            (M4_EXTRA_REPLAY_BUBBLE, 1),
            (M4_LD_RETURN_ALIGN, 7))
         m4_default(['M4_BRANCH_PRED'], ['two_bit'])
         m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
      ']
   )

SandPiper supports a number of --fmt* options that control the formatting of the generated Verilog. It would be nice to provide access in the configurator to these options. (This would, of course, be useful from Makerchip as well.)

Configurator tweaks:

• Add a button under "Get your code" to "View Below" that scrolls down (just to highlight the fact that the code is right there for the viewing).
• For "UI Configuration" and "Macro Configuration", create images that are zoomed-in and cropped.
• If the image is clear enough, remove "UI Configuration" button.
• Let's add some explanation to the compilation steps, somehow without cluttering things. The explanation is really about the arrows, so maybe the arrows can be more prominent with popup text? The text can be:
  • Your configuration selections are codified.
  • A macro-preprocessor (M4) applies parameters and instantiates components.
  • Redwood EDA's SandPiper(TM) SaaS Edition expands your Transaction-Level Verilog code into Verilog.
• For the selected file, add buttons: "Download File" and "Edit this File in Makerchip (as source code)", with corresponding functionality. With the addition of the button, you can remove the text: "After generation, any of these can be taken as source and modified by hand."
• Provide a minimum size on the code window (or other form of padding) to avoid having the window jump around as the bottom of the page changes position.
• Add a footer with github/redwoodeda links. "Dig deeper in the github repository", "Courtesy of Redwood EDA"--something like that.