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License: Apache License 2.0
AMBA AXI VIP
License: Apache License 2.0
Original issue is #16.
The uvm reg adapter needs to support not only AXI4-Lite but also AXI4.
To support AXI4, following changes are needed.
bust size
and bust length
fieldsid
fieldrw.n_bits
and lower address bits
configuration
object may be needed to get bus width
I have a problem with randomize(). Is it problem with my linux or something else?
When i use rendomize() in my project i don't have such error...
terminal output ------------------------------------------------------------------------>
if (!item.randomize() with {
|
xmsim: *W,SVRNDF (/home/tvip-axi/src/tvip_axi_slave_default_sequence.svh,59|22): The randomize method call failed. The unique id of the failed randomize call is 23.
xmsim: *F,RNDUNR: Randomization internal error, unexpected exception - 18rnc_eval_exception#6934
File - /dv/p4Cusers01nd/dvcmin_noida_legacy_rc_xcelium_092718_170012_linux/tbv/rnc/src/api/rnc_var.cpp:1977
var - SO = 2, U31, flags = ZESA, _value = 0x00000000 : data.size#5536 (/home/tvip-axi/src/tvip_axi_slave_default_sequence.svh, 59).
Hi Taichi,
I was searching for open-source AXI BFMs and landed onto your repository on github. This and your rggen is awesome piece of work and is very helpful. A big thank you to you for putting your hard work up there.
I am trying to use the verification elements for an all-AXI 2x3 switch where both the sides operate on AXI3/4.(I I've got experience in building backbones (AXI/APB/AHB etc) and worked on Vcs/NCVerilog before.)
I am trying to explore it more and trying to see how we can use it. I've got some questions about it -
Is it likely to work with iVerilog or Verilator or SV-Parser etc open-source Verilog simulators. There are VCS and Xcellium make files but we don't have those tools. Have you ever tried it. We gona try fresh, but in case you already know of issues here.
Will we able to use in an axi-switch verification environment...? In such a testbench, we need 2 AXI master BFMs, 3 AXI slave BFMs, protocol monitors and checkers and transactors plus testcases.
There are plenty of tasks and functions in the code and we are trying to read through and unwind them. But without a arch/document and the components, it's taking us some time. Hence the question.
Regards.
Add fixed and wrapping burst support.
To do this:
Hi, i try to run your default case.
but there is a error. the log is :
xwl@xwl-VirtualBox:~/prj/tvip-axi/sample/work$ make
make sim_vcs TEST=default
make[1]: Entering directory '/home/xwl/prj/tvip-axi/sample/work'
[ -f simv ] || (make compile_vcs)
make[2]: Entering directory '/home/xwl/prj/tvip-axi/sample/work'
vcs -full64 -lca -sverilog -l compile.log -timescale=1ns/1ps -ntb_opts uvm +define+UVM_NO_DEPRECATED+UVM_OBJECT_MUST_HAVE_CONSTRUCTO -top top -f /home/xwl/prj/tvip-axi/tue/compile.f -f /home/xwl/prj/tvip-axi/compile.f -f /home/xwl/prj/tvip-axi/sample/env/compile.f /home/xwl/prj/tvip-axi/sample/env/top.sv
/bin/sh: 0: Illegal option -h
vcs.mk:47: recipe for target 'compile_vcs' failed
make[2]: *** [compile_vcs] Error 2
make[2]: Leaving directory '/home/xwl/prj/tvip-axi/sample/work'
vcs.mk:43: recipe for target 'sim_vcs' failed
make[1]: *** [sim_vcs] Error 2
make[1]: Leaving directory '/home/xwl/prj/tvip-axi/sample/work'
makefile:30: recipe for target 'default' failed
make: *** [default] Error 2
Any suggestion?
xcelium でもサンプルを流せるように、xcelium 用の makefile を作る。
Hi,
I'm trying to build with Vivado 2020.1 and I'm seeing the following error:
ERROR: [VRFC 10-396] cannot assign a string to an unpacked type [/mnt/hgfs/test/projects/demo/tvip-axi/src/tvip_axi_monitor_base.svh:187]
WARNING: [VRFC 10-2663] foreach loop violates IEEE 1800 syntax [/mnt/hgfs/test/projects/demo/tvip-axi/tvip-common/src/tvip_item_waiter.svh:38]
Do you know why it's complaining with this?
I have encountered the following issue when tvip-axi is used as AXI4 memory slave.
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /path/to/tvip-axi/src/tvip_axi_payload_store.svh, line = 29, pos = 7
Scope: worklib.tvip_axi_pkg::tvip_axi_payload_store::store_response
Time: 4054 NS + 6
Verilog Stack Trace:
0: function worklib.tvip_axi_pkg::tvip_axi_payload_store::store_response at /path/to/tvip-axi/src/tvip_axi_payload_store.svh:29
1: task worklib.tvip_axi_pkg::tvip_axi_master_sub_driver@11260_6.sample_response at /path/to/tvip-axi/src/tvip_axi_master_driver.svh:256
2: task worklib.tvip_axi_pkg::tvip_axi_master_sub_driver@11260_6.response_thread at /path/to/tvip-axi/src/tvip_axi_master_driver.svh:207
3: process in worklib.tvip_axi_pkg::tvip_axi_master_sub_driver@11260_6.main at /path/to/tvip-axi/src/tvip_axi_master_driver.svh:91
The test sequence is:
Implement AXI4-Lite support.
Hi,
I picked up latest master branch to get W->AW master_driver change but it looks like latest code base is not backward compatible with what was there at the beginning of the year (are there any release names to talk about rather than dates?)
My question is, some of the AXI-4 signals are removed from the interface e.g. WID, AWLOCK etc. Is this intentional?
I am new to Github, is the only way to ask you any general questions is to open an issue?
For your UVM based AXI VIP, if we could compare with the those commercially provided from Cadence or Synopsys, how much percentage of the features are covered?
Your VIP is the only one available in open source and extremely impressive!
The latest version has another NULL pointer dereference as below:
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh, line = 521, pos = 14
Scope: worklib.uvm_pkg::uvm_transaction::get_event_pool
Time: 7134 NS + 13
Verilog Stack Trace:
0: function worklib.uvm_pkg::uvm_transaction::get_event_pool at /opt/eda/cadence/XCELIUM2103/tools/methodology/UVM/CDNS-1.2/sv/src/base/uvm_transaction.svh:521
1: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::get_event at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:41
2: function worklib.tue_pkg::tue_sequence_item_base#(uvm_pkg::uvm_sequence_item,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status,tvip_axi_pkg::tvip_axi_configuration,tvip_axi_pkg::tvip_axi_status)::ended at /path/to/tvip-axi/tue/src/seq/tue_sequence_item_base.svh:51
3: task worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.delay_thread at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:66
4: process in worklib.tvip_axi_pkg::tvip_axi_slave_driver_start_delay_consumer@13753_2.start_delay_thread.unmblk1 at /path/to/tvip-axi/src/tvip_axi_slave_driver.svh:48
The existing master driver can drive both AW & W at the same time or AW -> W but not W -> AW.
As per AMBA spec, this is a valid use case.
Hi Taichi Ishitani;
I have tried first run with your TVIP-AXI, however I have got the mismatch issue as follows:
UVM_ERROR /net/tvip-axi/sample/env/tvip_axi_sample_write_read_sequence.svh(74) @ 191000: uvm_test_top.master_agent.sequencer@@tvip_axi_sample_write_read_sequence [CMPDATA] write and read data are mismatched !!
The command I used is :
make sim_vcs TEST=default
If I forced the setting wstrb in tvip_axi_master_driver.svh to 'hffff as follows, the mismatch is gone.
vif.master_cb.wstrb <= 'hffff;
I am wondering that it is bug?
Thank you.
Regards
Nathan
Hi Taichi,
Is it possible that I have two in_agents driven by one sequencer in my env, one agent is TVIP-AXI and another one is my_agent for my DUT?
To support UVM RAL, implement RAL adapter and predictor.
Refer adapter and predictor for APB VIP.
@taichi-ishitani Thank you very much for your great work on this. I have just started to use your tvip-axi for AXI4-Lite master AXI4 slave memory agents. Implementation has just been completed and it works well, thanks.
For further improvement, the current tvip_axi_if cannot handle Z or X states because signals are declared as bit.
For example, AXI4 Lite master with tvip-axi cannot detect UVM_HAS_X status when reading registers with Z or X states.
I would like you to consider this issue in the future if you have some time.
書き込んだデータが読み出せない。
書き込みデータのモニターと取り出しが実装されていない。
Hi Taichi,
Can I use the MASTER and SLAVE of tvip-axi seperately in the project?
For example, I want to use the AXI-MASTER only in my poject. Can I call "tvip_axi_master_agent.svh" in my filelist and use the AXI-MASTER? Or are there any other files that I must included.
thanks
Hi Taichi,
Thanks for taking care of this project! I am trying to compile it with Vivado, but I have some problems with Xelab, so I need some help.
More specifically, I tried these versions and the following issues:
Completed static elaboration
ERROR: [XSIM 43-3316] Signal SIGSEGV received.
Printing stacktrace...
[0] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x75de43]
[1] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriFunctionCall&)+0x188) [0x7f793ff9df58]
[2] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x7593a0]
[3] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x75aad6]
[4] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriUnaryOperator&)+0xa9) [0x7f793ff93c99]
[5] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriConditionalStatement&)+0x1a9) [0x7f793ff98a19]
[6] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[7] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriSeqBlock&)+0xc4) [0x7f793ff97d34]
[8] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriConditionalStatement&)+0x181) [0x7f793ff989f1]
[9] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[10] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriSeqBlock&)+0xc4) [0x7f793ff97d34]
[11] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[12] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriTaskDecl&)+0xb9) [0x7f793ff98e29]
[13] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x75a173]
[14] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[15] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriClass&)+0x11b) [0x7f793ff99d3b]
[16] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[17] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriModule&)+0x98) [0x7f793ff98698]
[18] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x76248b]
[19] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x75ae30]
[20] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[21] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriFunctionDecl&)+0xef) [0x7f793ff9998f]
[22] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x75a1e3]
[23] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[24] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriClass&)+0x11b) [0x7f793ff99d3b]
[25] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[26] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriModule&)+0x98) [0x7f793ff98698]
[27] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x76248b]
[28] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x75a69a]
[29] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriSelectedName&)+0xb9) [0x7f793ff93559]
[30] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x75d963]
[31] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriScopeName&)+0x10) [0x7f793ff97160]
[32] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[33] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriImportDecl&)+0x138) [0x7f793ff9bfd8]
[34] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f793ff91d56]
[35] /tools/Xilinx/Vivado/2019.2/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::Visit(Verific::VeriModule&)+0x98) [0x7f793ff98698]
[36] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x76248b]
[37] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x76129c]
[38] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x4800da]
[39] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x45241d]
[40] /lib/x86_64-linux-gnu/libc.so.6(+0x29d90) [0x7f793ec00d90]
[41] /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0x80) [0x7f793ec00e40]
[42] /tools/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab() [0x46a3d0]
Done
I would really appreciate it if you can provide me with some ideas how to have at least one of these versions run correctly.
Thanks again for your support!
現状の実装では、xcelium で実行した場合、極端に実行時間が悪くなる。
プロファイルを取ってみると、ランダム制約の解決に殆どの時間が使われていることがわかった。
なので、ランダム制約を書き直し、実行時間を改善させる。
があると、制約の解決に時間がかかる模様。なので、これらを無くす方向で、ランダム制約を書き直す。
class `vseq(`tc_name) extends uvm_sequence;
`uvm_object_utils(`vseq(`tc_name))
`uvm_declare_p_sequencer(axi_test_vsqr)
function new(string name= "sanity_vseq");
super.new(name);
endfunction
virtual task body();
sanity_sequence dseq;
uvm_status_e status;
uvm_reg_data_t value;
if(starting_phase != null)
begin
starting_phase.raise_objection(this);
end
#10000;
dseq = sanity_sequence::type_id::create("dseq");
dseq.start(p_sequencer.p_axi_test_sqr);
#10000;
if(starting_phase != null)
begin
starting_phase.drop_objection(this);
end
endtask
endclass
Hi Taichi, I use the tvip-axi as a VIP in my project. It doesn't finish after this line dseq.start(p_sequencer.p_axi_test_sqr);
in my testcase. I wonder if there are something didn't finish in tvip-axi?
thanks
Cadence Xcelium doesn't support variable substitution in if-condition as follows:
if ((delay = get_address_ready_delay(item)) >= 0) begin
|
xmvlog: *E,EXPRPA (/path/to/tvip-axi/src/tvip_axi_slave_default_sequence.svh,32|15): expecting a right parenthesis (')') [4.3][9.7(IEEE)].
(`include file: /path/to/tvip-axi/src/tvip_axi_slave_default_sequence.svh line 32, file: /path/to/tvip-axi/src/tvip_axi_pkg.sv line 45)
This issue can be reproduced by the command:
cd sample/work
make compile_xcelium
Here is the detailed log:
tvip-axi_a516ccd_sample_work_compile_xcelium.log
Hi Taichi!
I have a problemlem connected with AXI Slave
After reset i see response on R channel...
I find a problem
https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L147
must delete in task
https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L196
protected task do_reset();
start_delay_consumer.do_reset();
...............................................
active_responses.delete();
active_ids.delete();
response_queue.delete(); <-------- !
reset_if();
@(posedge vif.areset_n);
endtask
patch for removing the `uvm_do macros since they are not supported in newer UVM versions.
現状、write/read の応答要求は 1 つのスレッドで処理する前提になっている。
write/read 同時に応答要求が来た場合、レースコンディションで、応答要求を取りこぼすことがある。
write/read 別スレッドで処理できるようにする。
In slave driver, if more than one wvalid is received before awvalid, only one bvalid is asserted, so the tests get stuck.
Hi @taichi-ishitani ! I have a problem when i have reset on AXI.
In my test I have AXI4 slave and DUT.
When i asserted reset the BValid, Bid not reset to zero.
The figure below
So i find the problem. I think it happened because of race conditions
https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_driver.svh#L524
this happened after
protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);
vif.slave_cb.bvalid <= valid;
if (valid) begin
vif.slave_cb.bid <= item.get_id();
vif.slave_cb.bresp <= item.get_response_status();
end
endtask
This
protected task reset_if();
vif.awready = configuration.default_awready;
vif.wready = configuration.default_wready;
vif.bvalid = '0;
vif.bid = '0;
vif.bresp = tvip_axi_response'(0);
endtask
So my decision
protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item);
vif.bvalid <= valid;
if (valid) begin
vif.bid <= item.get_id();
vif.bresp <= item.get_response_status();
end
endtask
I'm not sure, that I understand your logic correctly, but in my case, it's work fine...
Best regards.
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