efabless / raven-picorv32 Goto Github PK

Hi,

I was wondering whether the Raven_SPI was tested ? and in case it is not needed, what would be the safe way to get rid of the Raven_SPI without hurting the design ?

Thanks,

Hi,

I want to add an SPI interface to the SoC (hardware level) to communicate with any SPI slave interface.
I guess the SPI interfaces that already exist in the Raven design are for other purposes. So I was wondering what would be the best approach to integrate an SPI master interface to the design ? For instance, in case I don't need the Raven_SPI, do you think I can easily just turn it to a general purpose SPI interface ?

Thanks,

Is it possible to buy this proc and/or a devkit ?

The core itself is configurable, and the author shows the consumed resources of different configurations in its document:

Could you please tell me the configuration you use for the SoC?

Does this core runs Linux on it?

Can this entire SoC be simulated in Vivado?

Hi,
I am trying to run the iverilog simulation of the Raven-picorv32, however, as mentioned in your verilog code, iverilog does not support the aregc01_3v3 regulator module. What would be the best way to run the simulation without the regulator ?

Knowing that I am not interested in any analog part simulation, I need just an easy way to make sure that the SoC part is correctly working with the GPIOs.

I tried commenting the voltage regulator part and running the GPIO simulation, however, the GPIO states are not being reported correctly by the C program.

Many thanks