AXI Bridge about vexriscv

[Dolu1990]

Hi,

you want to generate the Verilog/Vhdl of the CPU and then continue in your flow ? or do a full design in SpinalHDL ?

If that's the first one, there is an example which generate the CPU and rework it's IO into AXI.

https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala

Sound good ?

[yannickl96]

Hello Dolu, I want to generate the Verilog of the CPU and then continue with Vivado to package the core and use it in a block design, therefore your example helped very much. I wonder how I could miss that. Thank you for your quick reply!