On a VexRiscv core without a Multiply or Divide stage, the core will execute a <code c

No trap generated for `divu` on core without divide,about spinalhdl/vexriscv

Comments (13)

Dolu1990 commented on May 23, 2024

https://github.com/xobs/VexRiscv-verilog/blob/riscv-contest-20190315/src/main/scala/vexriscv/GenCoreDefault.scala#L142 :) ?

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xobs commented on May 23, 2024

...I retract the statement. Sorry for the noise!

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Dolu1990 commented on May 23, 2024

No worries :)

Anyway, i will very soon merge the VexRiscv linux branch into master, it bringed a lot of fixes and compatibility improvements and better regressions test (including running linux on cache-less designs)

https://travis-ci.org/SpinalHDL/VexRiscv/builds/523267998

Just need to release the related SpinalHDL version, and update the readme

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xobs commented on May 23, 2024

Right now I'm mostly size-constrained. If I enable illegal instruction traps, it actually doesn't fit.

On a UP5K I have:

2-stage VexRiscV with 1024 bytes cache, 4 hardware breakpoints, and SIMPLE branch prediction
Memory-mapped Quad SPI Flash
Wishbone bus
Basic Timer
USB with five endpoints
Lattice LED Hard IP (memory-mapped)
8 kB ROM
Debugging via USB packets

The last part is the most exciting. I can debug a VexRiscV entirely without external tools over USB, while it's in the USB port. This includes debugging the USB stack, as long as it enumerates properly (i.e. the basic descriptors have to be transferred.)

Eventually I'll shrink the USB core, which will let me fit a more complicated VexRiscV. And hopefully Yosys will be able to infer the DSP blocks to do multiply.

But smaller is always better.

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Dolu1990 commented on May 23, 2024

Hoo nice :D
The cache is for the instruction ? The IBusCachedPlugin ?

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Dolu1990 commented on May 23, 2024

How much LC at the moment :D ?
Which frequancy ?

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xobs commented on May 23, 2024

Yes, IBusCachedPlugin as 1024 bytes. DBusCachedPlugin has 0 bytes.

Info: Device utilisation:
Info:            ICESTORM_LC:  5266/ 5280    99%
Info:           ICESTORM_RAM:    29/   30    96%
Info:                  SB_IO:    14/   96    14%
Info:                  SB_GB:     8/    8   100%
Info:           ICESTORM_PLL:     1/    1   100%
Info:            SB_WARMBOOT:     1/    1   100%
Info:           ICESTORM_DSP:     0/    8     0%
Info:         ICESTORM_HFOSC:     0/    1     0%
Info:         ICESTORM_LFOSC:     0/    1     0%
Info:                 SB_I2C:     0/    2     0%
Info:                 SB_SPI:     0/    2     0%
Info:                 IO_I3C:     0/    2     0%
Info:            SB_LEDDA_IP:     1/    1   100%
Info:            SB_RGBA_DRV:     1/    1   100%
Info:         ICESTORM_SPRAM:     4/    4   100%
...
Info: Max frequency for clock     'clk48': 200.80 MHz (PASS at 48.00 MHz)
Info: Max frequency for clock 'crg_clk12': 12.58 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock 'crg_clk48': 49.27 MHz (PASS at 48.00 MHz)

I think I mentioned that the VexRiscV has a very strange critical path that looks like a 32-bit adder. That's another thing I need to look into...

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Dolu1990 commented on May 23, 2024

wtf 99 % full, and still getting 12 Mhz
Nice :D

About weird 32 bits path, I do not remember about it, can you send and critical path report ?

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Dolu1990 commented on May 23, 2024

And the related netlist :D

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xobs commented on May 23, 2024

I'm pleasantly surprised that it's even able to route, let alone meet timing!

Here's the full output:

Info: Importing module top
Info: Rule checker, verifying imported design
Info: Checksum: 0x262d3f8b

Info: constrained 'clk48' to bel 'X6/Y0/io1'
Info: constrained 'spiflash_cs_n' to bel 'X24/Y0/io1'
Info: constrained 'spiflash_clk' to bel 'X24/Y0/io0'
Info: constrained 'spiflash_miso' to bel 'X23/Y0/io1'
Info: constrained 'spiflash_mosi' to bel 'X23/Y0/io0'
Info: constrained 'spiflash_wp' to bel 'X22/Y0/io1'
Info: constrained 'spiflash_hold' to bel 'X21/Y0/io1'
Info: constrained 'led_rgb0' to bel 'X4/Y31/io0'
Info: constrained 'led_rgb1' to bel 'X5/Y31/io0'
Info: constrained 'led_rgb2' to bel 'X6/Y31/io0'
Info: constrained 'usb_d_p' to bel 'X13/Y31/io1'
Info: constrained 'usb_d_n' to bel 'X13/Y31/io0'
Info: constrained 'usb_pullup' to bel 'X12/Y31/io1'
Info: constrained 'touch_t1' to bel 'X7/Y0/io0'
Info: constrained 'touch_t2' to bel 'X6/Y0/io0'
Info: constrained 'touch_t3' to bel 'X5/Y0/io0'
Info: constrained 'touch_t4' to bel 'X7/Y0/io1'
Warning: net 'usb_48_clk' does not exist in design, ignoring clock constraint
Warning: net 'usb_48_raw_clk' does not exist in design, ignoring clock constraint
Warning: net 'sys_clk' does not exist in design, ignoring clock constraint
Warning: net 'usb_12_clk' does not exist in design, ignoring clock constraint
Info: constraining clock net 'crg_clk48' to 48.00 MHz
Info: constraining clock net 'clk48' to 48.00 MHz
Warning: net 'crg_clk12_raw' does not exist in design, ignoring clock constraint

Info: Packing constants..
Info: Packing IOs..
Info: spiflash_cs_n feeds SB_IO SB_IO_4, removing $nextpnr_iobuf spiflash_cs_n.
Info: spiflash_clk feeds SB_IO SB_IO_5, removing $nextpnr_iobuf spiflash_clk.
Info: spiflash_miso feeds SB_IO SB_IO_3, removing $nextpnr_iobuf spiflash_miso.
Info: spiflash_mosi feeds SB_IO SB_IO_2, removing $nextpnr_iobuf spiflash_mosi.
Info: spiflash_wp feeds SB_IO SB_IO_6, removing $nextpnr_iobuf spiflash_wp.
Info: spiflash_hold feeds SB_IO SB_IO_7, removing $nextpnr_iobuf spiflash_hold.
Info: led_rgb0 use by SB_RGBA_DRV SB_RGBA_DRV, not creating SB_IO
Info: led_rgb1 use by SB_RGBA_DRV SB_RGBA_DRV, not creating SB_IO
Info: led_rgb2 use by SB_RGBA_DRV SB_RGBA_DRV, not creating SB_IO
Info: usb_d_p feeds SB_IO SB_IO, removing $nextpnr_iobuf usb_d_p.
Info: usb_d_n feeds SB_IO SB_IO_1, removing $nextpnr_iobuf usb_d_n.
Info: touch_t1 feeds SB_IO SB_IO_8, removing $nextpnr_iobuf touch_t1.
Info: touch_t2 feeds SB_IO SB_IO_9, removing $nextpnr_iobuf touch_t2.
Info: touch_t3 feeds SB_IO SB_IO_10, removing $nextpnr_iobuf touch_t3.
Info: touch_t4 feeds SB_IO SB_IO_11, removing $nextpnr_iobuf touch_t4.
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Packing carries..
Info: Packing RAMs..
Info: Placing PLLs..
Info:   constrained PLL 'SB_PLL40_CORE' to X12/Y31/pll_3
Info: Packing special functions..
Info:   constrained SB_LEDDA_IP 'SB_LEDDA_IP' to X0/Y31/ledda_ip_2
Info:   constrained SB_RGBA_DRV 'SB_RGBA_DRV' to X0/Y30/rgba_drv_0
Info: Promoting globals..
Info: promoting picorvspi_reset1 [reset] (fanout 763)
Info: promoting VexRiscv.reset [reset] (fanout 53)
Info: promoting $abc$53614$auto$rtlil.cc:1817:NotGate$53502 [reset] (fanout 32)
Info: promoting $abc$53614$auto$rtlil.cc:1817:NotGate$53490 [reset] (fanout 18)
Info: promoting VexRiscv.IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready [cen] (fanout 85)
Info: promoting $abc$53614$auto$dff2dffe.cc:158:make_patterns_logic$40950 [cen] (fanout 81)
Info: Constraining chains...
Info: Checksum: 0x4527e47a

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xe80bde5d

Info: Device utilisation:
Info:            ICESTORM_LC:  5266/ 5280    99%
Info:           ICESTORM_RAM:    29/   30    96%
Info:                  SB_IO:    14/   96    14%
Info:                  SB_GB:     8/    8   100%
Info:           ICESTORM_PLL:     1/    1   100%
Info:            SB_WARMBOOT:     1/    1   100%
Info:           ICESTORM_DSP:     0/    8     0%
Info:         ICESTORM_HFOSC:     0/    1     0%
Info:         ICESTORM_LFOSC:     0/    1     0%
Info:                 SB_I2C:     0/    2     0%
Info:                 SB_SPI:     0/    2     0%
Info:                 IO_I3C:     0/    2     0%
Info:            SB_LEDDA_IP:     1/    1   100%
Info:            SB_RGBA_DRV:     1/    1   100%
Info:         ICESTORM_SPRAM:     4/    4   100%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 4945 cells, random placement wirelen = 133370.
Info:     at initial placer iter 0, wirelen = 2401
Info:     at initial placer iter 1, wirelen = 2276
Info:     at initial placer iter 2, wirelen = 2401
Info:     at initial placer iter 3, wirelen = 2270
Info: Running main analytical placer.
Info:     at iteration #1, type ALL: wirelen solved = 2390, spread = 40378, legal = 65609; time = 1.89s
Info:     at iteration #2, type ALL: wirelen solved = 3966, spread = 33384, legal = 67077; time = 4.06s
Info:     at iteration #3, type ALL: wirelen solved = 5725, spread = 32622, legal = 60447; time = 2.23s
Info:     at iteration #4, type ALL: wirelen solved = 7580, spread = 32134, legal = 63270; time = 2.40s
Info:     at iteration #5, type ALL: wirelen solved = 8958, spread = 30878, legal = 57350; time = 1.81s
Info:     at iteration #6, type ALL: wirelen solved = 10182, spread = 28726, legal = 54201; time = 1.31s
Info:     at iteration #7, type ALL: wirelen solved = 11187, spread = 27001, legal = 53813; time = 2.00s
Info:     at iteration #8, type ALL: wirelen solved = 13235, spread = 26546, legal = 54741; time = 1.96s
Info:     at iteration #9, type ALL: wirelen solved = 13416, spread = 26820, legal = 56891; time = 1.86s
Info:     at iteration #10, type ALL: wirelen solved = 15466, spread = 26622, legal = 55555; time = 2.16s
Info:     at iteration #11, type ALL: wirelen solved = 15236, spread = 26706, legal = 54128; time = 1.39s
Info:     at iteration #12, type ALL: wirelen solved = 14986, spread = 27217, legal = 58582; time = 1.97s
Info: HeAP Placer Time: 27.72s
Info:   of which solving equations: 3.76s
Info:   of which spreading cells: 0.56s
Info:   of which strict legalisation: 21.54s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 407, wirelen = 53813
Info:   at iteration #5: temp = 0.000000, timing cost = 605, wirelen = 42556
Info:   at iteration #10: temp = 0.000000, timing cost = 528, wirelen = 39915
Info:   at iteration #15: temp = 0.000000, timing cost = 493, wirelen = 38514
Info:   at iteration #20: temp = 0.000000, timing cost = 479, wirelen = 37556
Info:   at iteration #25: temp = 0.000000, timing cost = 460, wirelen = 37191
Info:   at iteration #30: temp = 0.000000, timing cost = 466, wirelen = 37070
Info:   at iteration #34: temp = 0.000000, timing cost = 466, wirelen = 37037
Info: SA placement time 28.20s

Info: Max frequency for clock     'clk48': 228.05 MHz (PASS at 48.00 MHz)
Info: Max frequency for clock 'crg_clk12': 13.15 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock 'crg_clk48': 50.90 MHz (PASS at 48.00 MHz)

Info: Max delay <async>           -> posedge crg_clk12: 16.60 ns
Info: Max delay <async>           -> posedge crg_clk48: 13.04 ns
Info: Max delay posedge crg_clk12 -> <async>          : 18.27 ns
Info: Max delay posedge crg_clk12 -> posedge crg_clk48: 23.41 ns
Info: Max delay negedge crg_clk12 -> <async>          : 10.20 ns
Info: Max delay posedge crg_clk48 -> <async>          : 5.03 ns
Info: Max delay posedge crg_clk48 -> posedge crg_clk12: 28.40 ns

Info: Slack histogram:
Info:  legend: * represents 27 endpoint(s)
Info:          + represents [1,27) endpoint(s)
Info: [ -2581,   1558) |+
Info: [  1558,   5697) |*+
Info: [  5697,   9836) |*+
Info: [  9836,  13975) |**+
Info: [ 13975,  18114) |***+
Info: [ 18114,  22253) |*****+
Info: [ 22253,  26392) |*+
Info: [ 26392,  30531) |****+
Info: [ 30531,  34670) |****+
Info: [ 34670,  38809) |*****+
Info: [ 38809,  42948) |****+
Info: [ 42948,  47087) |**+
Info: [ 47087,  51226) |********+
Info: [ 51226,  55365) |************+
Info: [ 55365,  59504) |*************************************+
Info: [ 59504,  63643) |**********************************+
Info: [ 63643,  67782) |***********************+
Info: [ 67782,  71921) |*********************+
Info: [ 71921,  76060) |*********************+
Info: [ 76060,  80199) |************************************************************
Info: Checksum: 0x46db4797

Info: Routing..
Info: Setting up routing queue.
Info: Routing 16467 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs
Info:       1000 |       37        962 |   37   962 |     15508
Info:       2000 |       91       1908 |   54   946 |     14570
Info:       3000 |      231       2768 |  140   860 |     13743
Info:       4000 |      398       3601 |  167   833 |     12974
Info:       5000 |      567       4432 |  169   831 |     12206
Info:       6000 |      774       5225 |  207   793 |     11513
Info:       7000 |      997       6002 |  223   777 |     10838
Info:       8000 |     1196       6803 |  199   801 |     10142
Info:       9000 |     1413       7586 |  217   783 |      9438
Info:      10000 |     1746       8253 |  333   667 |      8999
Info:      11000 |     2031       8968 |  285   715 |      8439
Info:      12000 |     2319       9680 |  288   712 |      7884
Info:      13000 |     2734      10265 |  415   585 |      7520
Info:      14000 |     3080      10919 |  346   654 |      7050
Info:      15000 |     3585      11414 |  505   495 |      6821
Info:      16000 |     4049      11950 |  464   536 |      6544
Info:      17000 |     4498      12501 |  449   551 |      6247
Info:      18000 |     4901      13098 |  403   597 |      5862
Info:      19000 |     5350      13649 |  449   551 |      5555
Info:      20000 |     5934      14065 |  584   416 |      5419
Info:      21000 |     6496      14503 |  562   438 |      5317
Info:      22000 |     7023      14976 |  527   473 |      5136
Info:      23000 |     7567      15432 |  544   456 |      5085
Info:      24000 |     8087      15912 |  520   480 |      4950
Info:      25000 |     8641      16358 |  554   446 |      4874
Info:      26000 |     9149      16850 |  508   492 |      4719
Info:      27000 |     9679      17320 |  530   470 |      4512
Info:      28000 |    10193      17806 |  514   486 |      4371
Info:      29000 |    10720      18279 |  527   473 |      4168
Info:      30000 |    11183      18816 |  463   537 |      4067
Info:      31000 |    11703      19296 |  520   480 |      3920
Info:      32000 |    12300      19699 |  597   403 |      3869
Info:      33000 |    12851      20148 |  551   449 |      3841
Info:      34000 |    13436      20563 |  585   415 |      3783
Info:      35000 |    14036      20963 |  600   400 |      3705
Info:      36000 |    14577      21422 |  541   459 |      3618
Info:      37000 |    15139      21860 |  562   438 |      3505
Info:      38000 |    15697      22302 |  558   442 |      3493
Info:      39000 |    16232      22767 |  535   465 |      3408
Info:      40000 |    16777      23222 |  545   455 |      3331
Info:      41000 |    17350      23649 |  573   427 |      3155
Info:      42000 |    17948      24051 |  598   402 |      3105
Info:      43000 |    18529      24470 |  581   419 |      3070
Info:      44000 |    19089      24910 |  560   440 |      2904
Info:      45000 |    19661      25338 |  572   428 |      2860
Info:      46000 |    20276      25723 |  615   385 |      2836
Info:      47000 |    20913      26086 |  637   363 |      2791
Info:      48000 |    21524      26475 |  611   389 |      2768
Info:      49000 |    22115      26884 |  591   409 |      2755
Info:      50000 |    22690      27309 |  575   425 |      2737
Info:      51000 |    23283      27716 |  593   407 |      2702
Info:      52000 |    23917      28082 |  634   366 |      2683
Info:      53000 |    24546      28453 |  629   371 |      2667
Info:      54000 |    25117      28882 |  571   429 |      2651
Info:      55000 |    25744      29255 |  627   373 |      2625
Info:      56000 |    26389      29610 |  645   355 |      2621
Info:      57000 |    27010      29989 |  621   379 |      2579
Info:      58000 |    27604      30395 |  594   406 |      2536
Info:      59000 |    28216      30783 |  612   388 |      2512
Info:      60000 |    28856      31143 |  640   360 |      2477
Info:      61000 |    29458      31541 |  602   398 |      2443
Info:      62000 |    30070      31929 |  612   388 |      2442
Info:      63000 |    30688      32311 |  618   382 |      2418
Info:      64000 |    31239      32760 |  551   449 |      2410
Info:      65000 |    31840      33159 |  601   399 |      2412
Info:      66000 |    32472      33527 |  632   368 |      2410
Info:      67000 |    33109      33890 |  637   363 |      2377
Info:      68000 |    33672      34327 |  563   437 |      2375
Info:      69000 |    34324      34675 |  652   348 |      2398
Info:      70000 |    34945      35054 |  621   379 |      2387
Info:      71000 |    35568      35431 |  623   377 |      2358
Info:      72000 |    36190      35809 |  622   378 |      2342
Info:      73000 |    36816      36183 |  626   374 |      2309
Info:      74000 |    37464      36535 |  648   352 |      2308
Info:      75000 |    38043      36956 |  579   421 |      2280
Info:      76000 |    38653      37346 |  610   390 |      2272
Info:      77000 |    39300      37699 |  647   353 |      2282
Info:      78000 |    39893      38106 |  593   407 |      2263
Info:      79000 |    40479      38520 |  586   414 |      2228
Info:      80000 |    41100      38899 |  621   379 |      2204
Info:      81000 |    41731      39268 |  631   369 |      2181
Info:      82000 |    42375      39624 |  644   356 |      2198
Info:      83000 |    42958      40041 |  583   417 |      2172
Info:      84000 |    43601      40398 |  643   357 |      2157
Info:      85000 |    44264      40735 |  663   337 |      2147
Info:      86000 |    44856      41143 |  592   408 |      2128
Info:      87000 |    45503      41496 |  647   353 |      2122
Info:      88000 |    46137      41862 |  634   366 |      2101
Info:      89000 |    46758      42241 |  621   379 |      2106
Info:      90000 |    47421      42578 |  663   337 |      2060
Info:      91000 |    48050      42949 |  629   371 |      2033
Info:      92000 |    48643      43356 |  593   407 |      2002
Info:      93000 |    49304      43695 |  661   339 |      2001
Info:      94000 |    49928      44071 |  624   376 |      1977
Info:      95000 |    50601      44398 |  673   327 |      1963
Info:      96000 |    51208      44791 |  607   393 |      1963
Info:      97000 |    51843      45156 |  635   365 |      1931
Info:      98000 |    52452      45547 |  609   391 |      1917
Info:      99000 |    53063      45936 |  611   389 |      1866
Info:     100000 |    53675      46324 |  612   388 |      1856
Info:     101000 |    54316      46683 |  641   359 |      1860
Info:     102000 |    54932      47067 |  616   384 |      1848
Info:     103000 |    55587      47412 |  655   345 |      1855
Info:     104000 |    56261      47738 |  674   326 |      1822
Info:     105000 |    56886      48113 |  625   375 |      1809
Info:     106000 |    57542      48457 |  656   344 |      1788
Info:     107000 |    58164      48835 |  622   378 |      1792
Info:     108000 |    58802      49197 |  638   362 |      1785
Info:     109000 |    59464      49535 |  662   338 |      1773
Info:     110000 |    60135      49864 |  671   329 |      1766
Info:     111000 |    60740      50259 |  605   395 |      1786
Info:     112000 |    61394      50605 |  654   346 |      1744
Info:     113000 |    62044      50955 |  650   350 |      1728
Info:     114000 |    62653      51346 |  609   391 |      1758
Info:     115000 |    63280      51719 |  627   373 |      1704
Info:     116000 |    63935      52064 |  655   345 |      1677
Info:     117000 |    64566      52433 |  631   369 |      1709
Info:     118000 |    65244      52755 |  678   322 |      1693
Info:     119000 |    65833      53166 |  589   411 |      1680
Info:     120000 |    66428      53571 |  595   405 |      1653
Info:     121000 |    67036      53963 |  608   392 |      1641
Info:     122000 |    67703      54296 |  667   333 |      1628
Info:     123000 |    68325      54674 |  622   378 |      1641
Info:     124000 |    68973      55026 |  648   352 |      1626
Info:     125000 |    69634      55365 |  661   339 |      1629
Info:     126000 |    70279      55720 |  645   355 |      1639
Info:     127000 |    70904      56095 |  625   375 |      1648
Info:     128000 |    71569      56430 |  665   335 |      1656
Info:     129000 |    72198      56801 |  629   371 |      1625
Info:     130000 |    72864      57135 |  666   334 |      1596
Info:     131000 |    73499      57500 |  635   365 |      1558
Info:     132000 |    74114      57885 |  615   385 |      1559
Info:     133000 |    74762      58237 |  648   352 |      1513
Info:     134000 |    75401      58598 |  639   361 |      1504
Info:     135000 |    76065      58934 |  664   336 |      1485
Info:     136000 |    76750      59249 |  685   315 |      1480
Info:     137000 |    77432      59567 |  682   318 |      1468
Info:     138000 |    78069      59930 |  637   363 |      1461
Info:     139000 |    78709      60290 |  640   360 |      1473
Info:     140000 |    79372      60627 |  663   337 |      1455
Info:     141000 |    80102      60897 |  730   270 |      1420
Info:     142000 |    80696      61303 |  594   406 |      1230
Info:     143000 |    81291      61708 |  595   405 |       984
Info:     144000 |    81969      62030 |  678   322 |       986
Info:     145000 |    82600      62399 |  631   369 |       844
Info:     146000 |    83086      62913 |  486   514 |       686
Info:     147000 |    83598      63401 |  512   488 |       500
Info:     148000 |    84195      63804 |  597   403 |       382
Info:     149000 |    84818      64181 |  623   377 |       327
Info:     149905 |    85212      64693 |  394   512 |         0
Info: Routing complete.
Info: Route time 328.80s
Info: Checksum: 0x234c366f

Info: Critical path report for clock 'clk48' (posedge -> posedge):
Info: curr total
Info:  1.4  1.4  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56810_LC.O
Info:  2.4  3.8    Net crg_clk12_counter[1] budget 18.261999 ns (12,2) -> (12,2)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56810_LC.I1
Info:  1.2  5.0  Setup $abc$53614$auto$blifparse.cc:492:parse_blif$56810_LC.I1
Info: 2.6 ns logic, 2.4 ns routing

Info: Critical path report for clock 'crg_clk12' (posedge -> posedge):
Info: curr total
Info:  1.4  1.4  Source $auto$simplemap.cc:420:simplemap_dff$17320_DFFLC.O
Info:  4.0  5.4    Net VexRiscv._zz_221_[4] budget -0.305000 ns (3,21) -> (12,19)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56886_LC.I0
Info:  1.3  6.7  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56886_LC.O
Info:  1.8  8.5    Net $abc$53614$n7789 budget -0.044000 ns (12,19) -> (12,18)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56887_LC.I3
Info:  0.9  9.3  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56887_LC.O
Info:  4.9 14.2    Net $abc$53614$techmap\VexRiscv.$not$D:\Code\Fomu\foboot\hw\2-stage-1024-cache-debug.v:1190$1529_Y[4] budget 1.933000 ns (12,18) -> (17,5)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56245_LC.I0
Info:  1.3 15.5  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56245_LC.O
Info:  3.0 18.5    Net VexRiscv._zz_226_[4] budget 1.209000 ns (17,5) -> (15,5)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[4].adder_LC.I1
Info:  0.7 19.2  Source $auto$maccmap.cc:240:synth$15411.slice[4].adder_LC.COUT
Info:  0.0 19.2    Net $auto$maccmap.cc:240:synth$15411.C[5] budget 0.000000 ns (15,5) -> (15,5)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[5].adder_LC.CIN
Info:  0.3 19.5  Source $auto$maccmap.cc:240:synth$15411.slice[5].adder_LC.COUT
Info:  0.0 19.5    Net $auto$maccmap.cc:240:synth$15411.C[6] budget 0.000000 ns (15,5) -> (15,5)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[6].adder_LC.CIN
Info:  0.3 19.8  Source $auto$maccmap.cc:240:synth$15411.slice[6].adder_LC.COUT
Info:  0.6 20.3    Net $auto$maccmap.cc:240:synth$15411.C[7] budget 0.560000 ns (15,5) -> (15,6)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[7].adder_LC.CIN
Info:  0.3 20.6  Source $auto$maccmap.cc:240:synth$15411.slice[7].adder_LC.COUT
Info:  0.0 20.6    Net $auto$maccmap.cc:240:synth$15411.C[8] budget 0.000000 ns (15,6) -> (15,6)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[8].adder_LC.CIN
Info:  0.3 20.9  Source $auto$maccmap.cc:240:synth$15411.slice[8].adder_LC.COUT
Info:  0.0 20.9    Net $auto$maccmap.cc:240:synth$15411.C[9] budget 0.000000 ns (15,6) -> (15,6)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[9].adder_LC.CIN
Info:  0.3 21.1  Source $auto$maccmap.cc:240:synth$15411.slice[9].adder_LC.COUT
Info:  0.0 21.1    Net $auto$maccmap.cc:240:synth$15411.C[10] budget 0.000000 ns (15,6) -> (15,6)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[10].adder_LC.CIN
Info:  0.3 21.4  Source $auto$maccmap.cc:240:synth$15411.slice[10].adder_LC.COUT
Info:  0.0 21.4    Net $auto$maccmap.cc:240:synth$15411.C[11] budget 0.000000 ns (15,6) -> (15,6)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[11].adder_LC.CIN
Info:  0.3 21.7  Source $auto$maccmap.cc:240:synth$15411.slice[11].adder_LC.COUT
Info:  0.0 21.7    Net $auto$maccmap.cc:240:synth$15411.C[12] budget 0.000000 ns (15,6) -> (15,6)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[12].adder_LC.CIN
Info:  0.3 22.0  Source $auto$maccmap.cc:240:synth$15411.slice[12].adder_LC.COUT
Info:  0.0 22.0    Net $auto$maccmap.cc:240:synth$15411.C[13] budget 0.000000 ns (15,6) -> (15,6)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[13].adder_LC.CIN
Info:  0.3 22.3  Source $auto$maccmap.cc:240:synth$15411.slice[13].adder_LC.COUT
Info:  0.0 22.3    Net $auto$maccmap.cc:240:synth$15411.C[14] budget 0.000000 ns (15,6) -> (15,6)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[14].adder_LC.CIN
Info:  0.3 22.5  Source $auto$maccmap.cc:240:synth$15411.slice[14].adder_LC.COUT
Info:  0.6 23.1    Net $auto$maccmap.cc:240:synth$15411.C[15] budget 0.560000 ns (15,6) -> (15,7)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[15].adder_LC.CIN
Info:  0.3 23.4  Source $auto$maccmap.cc:240:synth$15411.slice[15].adder_LC.COUT
Info:  0.0 23.4    Net $auto$maccmap.cc:240:synth$15411.C[16] budget 0.000000 ns (15,7) -> (15,7)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[16].adder_LC.CIN
Info:  0.3 23.6  Source $auto$maccmap.cc:240:synth$15411.slice[16].adder_LC.COUT
Info:  0.0 23.6    Net $auto$maccmap.cc:240:synth$15411.C[17] budget 0.000000 ns (15,7) -> (15,7)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[17].adder_LC.CIN
Info:  0.3 23.9  Source $auto$maccmap.cc:240:synth$15411.slice[17].adder_LC.COUT
Info:  0.0 23.9    Net $auto$maccmap.cc:240:synth$15411.C[18] budget 0.000000 ns (15,7) -> (15,7)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[18].adder_LC.CIN
Info:  0.3 24.2  Source $auto$maccmap.cc:240:synth$15411.slice[18].adder_LC.COUT
Info:  0.0 24.2    Net $auto$maccmap.cc:240:synth$15411.C[19] budget 0.000000 ns (15,7) -> (15,7)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[19].adder_LC.CIN
Info:  0.3 24.5  Source $auto$maccmap.cc:240:synth$15411.slice[19].adder_LC.COUT
Info:  0.0 24.5    Net $auto$maccmap.cc:240:synth$15411.C[20] budget 0.000000 ns (15,7) -> (15,7)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[20].adder_LC.CIN
Info:  0.3 24.8  Source $auto$maccmap.cc:240:synth$15411.slice[20].adder_LC.COUT
Info:  0.0 24.8    Net $auto$maccmap.cc:240:synth$15411.C[21] budget 0.000000 ns (15,7) -> (15,7)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[21].adder_LC.CIN
Info:  0.3 25.0  Source $auto$maccmap.cc:240:synth$15411.slice[21].adder_LC.COUT
Info:  0.0 25.0    Net $auto$maccmap.cc:240:synth$15411.C[22] budget 0.000000 ns (15,7) -> (15,7)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[22].adder_LC.CIN
Info:  0.3 25.3  Source $auto$maccmap.cc:240:synth$15411.slice[22].adder_LC.COUT
Info:  0.6 25.9    Net $auto$maccmap.cc:240:synth$15411.C[23] budget 0.560000 ns (15,7) -> (15,8)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[23].adder_LC.CIN
Info:  0.3 26.1  Source $auto$maccmap.cc:240:synth$15411.slice[23].adder_LC.COUT
Info:  0.0 26.1    Net $auto$maccmap.cc:240:synth$15411.C[24] budget 0.000000 ns (15,8) -> (15,8)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[24].adder_LC.CIN
Info:  0.3 26.4  Source $auto$maccmap.cc:240:synth$15411.slice[24].adder_LC.COUT
Info:  0.0 26.4    Net $auto$maccmap.cc:240:synth$15411.C[25] budget 0.000000 ns (15,8) -> (15,8)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[25].adder_LC.CIN
Info:  0.3 26.7  Source $auto$maccmap.cc:240:synth$15411.slice[25].adder_LC.COUT
Info:  0.0 26.7    Net $auto$maccmap.cc:240:synth$15411.C[26] budget 0.000000 ns (15,8) -> (15,8)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[26].adder_LC.CIN
Info:  0.3 27.0  Source $auto$maccmap.cc:240:synth$15411.slice[26].adder_LC.COUT
Info:  0.0 27.0    Net $auto$maccmap.cc:240:synth$15411.C[27] budget 0.000000 ns (15,8) -> (15,8)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[27].adder_LC.CIN
Info:  0.3 27.3  Source $auto$maccmap.cc:240:synth$15411.slice[27].adder_LC.COUT
Info:  0.0 27.3    Net $auto$maccmap.cc:240:synth$15411.C[28] budget 0.000000 ns (15,8) -> (15,8)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[28].adder_LC.CIN
Info:  0.3 27.5  Source $auto$maccmap.cc:240:synth$15411.slice[28].adder_LC.COUT
Info:  0.0 27.5    Net $auto$maccmap.cc:240:synth$15411.C[29] budget 0.000000 ns (15,8) -> (15,8)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[29].adder_LC.CIN
Info:  0.3 27.8  Source $auto$maccmap.cc:240:synth$15411.slice[29].adder_LC.COUT
Info:  0.0 27.8    Net $auto$maccmap.cc:240:synth$15411.C[30] budget 0.000000 ns (15,8) -> (15,8)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[30].adder_LC.CIN
Info:  0.3 28.1  Source $auto$maccmap.cc:240:synth$15411.slice[30].adder_LC.COUT
Info:  1.2 29.3    Net $auto$maccmap.cc:240:synth$15411.C[31] budget 1.220000 ns (15,8) -> (15,9)
Info:                Sink $auto$maccmap.cc:240:synth$15411.slice[31].adder_LC.I3
Info:  0.9 30.2  Source $auto$maccmap.cc:240:synth$15411.slice[31].adder_LC.O
Info:  1.8 31.9    Net VexRiscv._zz_223_[31] budget 1.710000 ns (15,9) -> (14,9)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$54046_LC.I2
Info:  1.2 33.1  Source $abc$53614$auto$blifparse.cc:492:parse_blif$54046_LC.O
Info:  1.8 34.9    Net $abc$53614$techmap\VexRiscv.$logic_not$D:\Code\Fomu\foboot\hw\2-stage-1024-cache-debug.v:2768$1825_Y_inv budget 0.927000 ns (14,9) -> (13,10)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$54045_LC.I1
Info:  1.2 36.1  Source $abc$53614$auto$blifparse.cc:492:parse_blif$54045_LC.O
Info:  2.3 38.4    Net $abc$53614$n4450 budget 0.927000 ns (13,10) -> (10,10)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$53919_LC.I0
Info:  1.3 39.7  Source $abc$53614$auto$blifparse.cc:492:parse_blif$53919_LC.O
Info:  1.8 41.5    Net $abc$53614$n4307 budget 1.464000 ns (10,10) -> (9,11)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56003_LC.I0
Info:  1.3 42.8  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56003_LC.O
Info:  1.8 44.5    Net $abc$53614$n6718 budget 0.219000 ns (9,11) -> (9,11)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56006_LC.I0
Info:  1.3 45.8  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56006_LC.O
Info:  1.8 47.6    Net $abc$53614$techmap\VexRiscv.$logic_and$D:\Code\Fomu\foboot\hw\2-stage-1024-cache-debug.v:2879$1839_Y_inv budget 0.359000 ns (9,11) -> (8,10)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56005_LC.I0
Info:  1.3 48.9  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56005_LC.O
Info:  1.8 50.6    Net $abc$53614$n6720 budget 1.103000 ns (8,10) -> (7,10)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56004_LC.I2
Info:  1.2 51.8  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56004_LC.O
Info:  1.8 53.6    Net VexRiscv.execute_BranchPlugin_branch_src2[2] budget 1.241000 ns (7,10) -> (8,11)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[2].adder_LC.I2
Info:  0.6 54.2  Source $auto$alumacc.cc:474:replace_alu$7185.slice[2].adder_LC.COUT
Info:  0.0 54.2    Net $auto$alumacc.cc:474:replace_alu$7185.C[3] budget 0.000000 ns (8,11) -> (8,11)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[3].adder_LC.CIN
Info:  0.3 54.5  Source $auto$alumacc.cc:474:replace_alu$7185.slice[3].adder_LC.COUT
Info:  0.0 54.5    Net $auto$alumacc.cc:474:replace_alu$7185.C[4] budget 0.000000 ns (8,11) -> (8,11)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[4].adder_LC.CIN
Info:  0.3 54.8  Source $auto$alumacc.cc:474:replace_alu$7185.slice[4].adder_LC.COUT
Info:  0.0 54.8    Net $auto$alumacc.cc:474:replace_alu$7185.C[5] budget 0.000000 ns (8,11) -> (8,11)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[5].adder_LC.CIN
Info:  0.3 55.0  Source $auto$alumacc.cc:474:replace_alu$7185.slice[5].adder_LC.COUT
Info:  0.0 55.0    Net $auto$alumacc.cc:474:replace_alu$7185.C[6] budget 0.000000 ns (8,11) -> (8,11)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[6].adder_LC.CIN
Info:  0.3 55.3  Source $auto$alumacc.cc:474:replace_alu$7185.slice[6].adder_LC.COUT
Info:  0.0 55.3    Net $auto$alumacc.cc:474:replace_alu$7185.C[7] budget 0.000000 ns (8,11) -> (8,11)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[7].adder_LC.CIN
Info:  0.3 55.6  Source $auto$alumacc.cc:474:replace_alu$7185.slice[7].adder_LC.COUT
Info:  0.6 56.1    Net $auto$alumacc.cc:474:replace_alu$7185.C[8] budget 0.560000 ns (8,11) -> (8,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[8].adder_LC.CIN
Info:  0.3 56.4  Source $auto$alumacc.cc:474:replace_alu$7185.slice[8].adder_LC.COUT
Info:  0.0 56.4    Net $auto$alumacc.cc:474:replace_alu$7185.C[9] budget 0.000000 ns (8,12) -> (8,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[9].adder_LC.CIN
Info:  0.3 56.7  Source $auto$alumacc.cc:474:replace_alu$7185.slice[9].adder_LC.COUT
Info:  0.0 56.7    Net $auto$alumacc.cc:474:replace_alu$7185.C[10] budget 0.000000 ns (8,12) -> (8,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[10].adder_LC.CIN
Info:  0.3 57.0  Source $auto$alumacc.cc:474:replace_alu$7185.slice[10].adder_LC.COUT
Info:  0.0 57.0    Net $auto$alumacc.cc:474:replace_alu$7185.C[11] budget 0.000000 ns (8,12) -> (8,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[11].adder_LC.CIN
Info:  0.3 57.3  Source $auto$alumacc.cc:474:replace_alu$7185.slice[11].adder_LC.COUT
Info:  0.0 57.3    Net $auto$alumacc.cc:474:replace_alu$7185.C[12] budget 0.000000 ns (8,12) -> (8,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[12].adder_LC.CIN
Info:  0.3 57.5  Source $auto$alumacc.cc:474:replace_alu$7185.slice[12].adder_LC.COUT
Info:  0.0 57.5    Net $auto$alumacc.cc:474:replace_alu$7185.C[13] budget 0.000000 ns (8,12) -> (8,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[13].adder_LC.CIN
Info:  0.3 57.8  Source $auto$alumacc.cc:474:replace_alu$7185.slice[13].adder_LC.COUT
Info:  0.0 57.8    Net $auto$alumacc.cc:474:replace_alu$7185.C[14] budget 0.000000 ns (8,12) -> (8,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[14].adder_LC.CIN
Info:  0.3 58.1  Source $auto$alumacc.cc:474:replace_alu$7185.slice[14].adder_LC.COUT
Info:  0.0 58.1    Net $auto$alumacc.cc:474:replace_alu$7185.C[15] budget 0.000000 ns (8,12) -> (8,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[15].adder_LC.CIN
Info:  0.3 58.4  Source $auto$alumacc.cc:474:replace_alu$7185.slice[15].adder_LC.COUT
Info:  0.6 58.9    Net $auto$alumacc.cc:474:replace_alu$7185.C[16] budget 0.560000 ns (8,12) -> (8,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[16].adder_LC.CIN
Info:  0.3 59.2  Source $auto$alumacc.cc:474:replace_alu$7185.slice[16].adder_LC.COUT
Info:  0.0 59.2    Net $auto$alumacc.cc:474:replace_alu$7185.C[17] budget 0.000000 ns (8,13) -> (8,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[17].adder_LC.CIN
Info:  0.3 59.5  Source $auto$alumacc.cc:474:replace_alu$7185.slice[17].adder_LC.COUT
Info:  0.0 59.5    Net $auto$alumacc.cc:474:replace_alu$7185.C[18] budget 0.000000 ns (8,13) -> (8,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[18].adder_LC.CIN
Info:  0.3 59.8  Source $auto$alumacc.cc:474:replace_alu$7185.slice[18].adder_LC.COUT
Info:  0.0 59.8    Net $auto$alumacc.cc:474:replace_alu$7185.C[19] budget 0.000000 ns (8,13) -> (8,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[19].adder_LC.CIN
Info:  0.3 60.0  Source $auto$alumacc.cc:474:replace_alu$7185.slice[19].adder_LC.COUT
Info:  0.0 60.0    Net $auto$alumacc.cc:474:replace_alu$7185.C[20] budget 0.000000 ns (8,13) -> (8,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[20].adder_LC.CIN
Info:  0.3 60.3  Source $auto$alumacc.cc:474:replace_alu$7185.slice[20].adder_LC.COUT
Info:  0.0 60.3    Net $auto$alumacc.cc:474:replace_alu$7185.C[21] budget 0.000000 ns (8,13) -> (8,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[21].adder_LC.CIN
Info:  0.3 60.6  Source $auto$alumacc.cc:474:replace_alu$7185.slice[21].adder_LC.COUT
Info:  0.0 60.6    Net $auto$alumacc.cc:474:replace_alu$7185.C[22] budget 0.000000 ns (8,13) -> (8,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[22].adder_LC.CIN
Info:  0.3 60.9  Source $auto$alumacc.cc:474:replace_alu$7185.slice[22].adder_LC.COUT
Info:  0.0 60.9    Net $auto$alumacc.cc:474:replace_alu$7185.C[23] budget 0.000000 ns (8,13) -> (8,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[23].adder_LC.CIN
Info:  0.3 61.1  Source $auto$alumacc.cc:474:replace_alu$7185.slice[23].adder_LC.COUT
Info:  0.6 61.7    Net $auto$alumacc.cc:474:replace_alu$7185.C[24] budget 0.560000 ns (8,13) -> (8,14)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[24].adder_LC.CIN
Info:  0.3 62.0  Source $auto$alumacc.cc:474:replace_alu$7185.slice[24].adder_LC.COUT
Info:  0.0 62.0    Net $auto$alumacc.cc:474:replace_alu$7185.C[25] budget 0.000000 ns (8,14) -> (8,14)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[25].adder_LC.CIN
Info:  0.3 62.3  Source $auto$alumacc.cc:474:replace_alu$7185.slice[25].adder_LC.COUT
Info:  0.0 62.3    Net $auto$alumacc.cc:474:replace_alu$7185.C[26] budget 0.000000 ns (8,14) -> (8,14)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[26].adder_LC.CIN
Info:  0.3 62.5  Source $auto$alumacc.cc:474:replace_alu$7185.slice[26].adder_LC.COUT
Info:  0.0 62.5    Net $auto$alumacc.cc:474:replace_alu$7185.C[27] budget 0.000000 ns (8,14) -> (8,14)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[27].adder_LC.CIN
Info:  0.3 62.8  Source $auto$alumacc.cc:474:replace_alu$7185.slice[27].adder_LC.COUT
Info:  0.0 62.8    Net $auto$alumacc.cc:474:replace_alu$7185.C[28] budget 0.000000 ns (8,14) -> (8,14)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[28].adder_LC.CIN
Info:  0.3 63.1  Source $auto$alumacc.cc:474:replace_alu$7185.slice[28].adder_LC.COUT
Info:  0.0 63.1    Net $auto$alumacc.cc:474:replace_alu$7185.C[29] budget 0.000000 ns (8,14) -> (8,14)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[29].adder_LC.CIN
Info:  0.3 63.4  Source $auto$alumacc.cc:474:replace_alu$7185.slice[29].adder_LC.COUT
Info:  0.0 63.4    Net $auto$alumacc.cc:474:replace_alu$7185.C[30] budget 0.000000 ns (8,14) -> (8,14)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[30].adder_LC.CIN
Info:  0.3 63.7  Source $auto$alumacc.cc:474:replace_alu$7185.slice[30].adder_LC.COUT
Info:  0.7 64.3    Net $auto$alumacc.cc:474:replace_alu$7185.C[31] budget 0.660000 ns (8,14) -> (8,14)
Info:                Sink $auto$alumacc.cc:474:replace_alu$7185.slice[31].adder_LC.I3
Info:  0.9 65.2  Source $auto$alumacc.cc:474:replace_alu$7185.slice[31].adder_LC.O
Info:  3.0 68.1    Net VexRiscv._zz_25_[31] budget 1.692000 ns (8,14) -> (5,12)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$57088_LC.I1
Info:  1.2 69.4  Source $abc$53614$auto$blifparse.cc:492:parse_blif$57088_LC.O
Info:  1.8 71.1    Net $abc$53614$n8049 budget 1.434000 ns (5,12) -> (5,13)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$57191_LC.I3
Info:  0.9 72.0  Source $abc$53614$auto$blifparse.cc:492:parse_blif$57191_LC.O
Info:  6.3 78.3    Net $abc$53614$VexRiscv.IBusCachedPlugin_jump_pcLoad_payload[31]_inv budget 2.930000 ns (5,13) -> (20,22)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$57090_LC.I0
Info:  1.2 79.5  Setup $abc$53614$auto$blifparse.cc:492:parse_blif$57090_LC.I0
Info: 35.0 ns logic, 44.5 ns routing

Info: Critical path report for clock 'crg_clk48' (posedge -> posedge):
Info: curr total
Info:  1.4  1.4  Source $auto$simplemap.cc:420:simplemap_dff$15834_DFFLC.O
Info:  1.8  3.2    Net usb_usb_core_rx_graycounter0_q[3] budget 0.400000 ns (22,27) -> (23,28)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$55424_LC.I0
Info:  1.3  4.4  Source $abc$53614$auto$blifparse.cc:492:parse_blif$55424_LC.O
Info:  1.8  6.2    Net $abc$53614$eq$top.v:1878$185_Y budget -0.217000 ns (23,28) -> (23,27)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$55423_LC.I0
Info:  1.3  7.5  Source $abc$53614$auto$blifparse.cc:492:parse_blif$55423_LC.O
Info:  1.8  9.2    Net $abc$53614$n6054 budget 0.401000 ns (23,27) -> (23,26)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$55422_LC.I0
Info:  1.3 10.5  Source $abc$53614$auto$blifparse.cc:492:parse_blif$55422_LC.O
Info:  1.8 12.3    Net $abc$53614$usb_usb_core_rx_graycounter0_ce budget 1.300000 ns (23,26) -> (22,25)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56458_LC.I2
Info:  1.2 13.5  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56458_LC.O
Info:  5.6 19.1    Net $abc$53614$auto$dff2dffe.cc:158:make_patterns_logic$32034 budget 2.160000 ns (22,25) -> (21,6)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56459_LC.I2
Info:  1.2 20.3  Setup $abc$53614$auto$blifparse.cc:492:parse_blif$56459_LC.I2
Info: 7.6 ns logic, 12.7 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge crg_clk12':
Info: curr total
Info:  0.0  0.0  Source SB_IO_7.D_IN_0
Info:  3.0  3.0    Net csrbank1_stat1_w[3] budget 18.823999 ns (21,0) -> (23,4)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56281_LC.I3
Info:  0.9  3.8  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56281_LC.O
Info:  3.0  6.8    Net $abc$53614$n7144 budget 16.837999 ns (23,4) -> (23,10)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56280_LC.I3
Info:  0.9  7.7  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56280_LC.O
Info:  1.8  9.5    Net $abc$53614$n7143 budget 16.837999 ns (23,10) -> (23,10)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56279_LC.I2
Info:  1.2 10.7  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56279_LC.O
Info:  3.5 14.2    Net $abc$53614$n7142 budget 19.205999 ns (23,10) -> (18,12)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56278_LC.I0
Info:  1.2 15.4  Setup $abc$53614$auto$blifparse.cc:492:parse_blif$56278_LC.I0
Info: 4.2 ns logic, 11.2 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge crg_clk48':
Info: curr total
Info:  0.0  0.0  Source SB_IO_1.D_IN_0
Info:  3.9  3.9    Net usb_iobuf_usb_n_rx_io budget 4.900000 ns (13,31) -> (21,30)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56503_LC.I1
Info:  1.2  5.1  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56503_LC.O
Info:  3.1  8.2    Net $abc$53614$auto$simplemap.cc:309:simplemap_lut$15132[1]_inv budget -0.886000 ns (21,30) -> (21,25)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56501_LC.I2
Info:  1.2  9.4  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56501_LC.O
Info:  1.8 11.1    Net $abc$53614$n7381 budget 0.279000 ns (21,25) -> (20,25)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56499_LC.I2
Info:  1.2 12.3  Setup $abc$53614$auto$blifparse.cc:492:parse_blif$56499_LC.I2
Info: 3.6 ns logic, 8.7 ns routing

Info: Critical path report for cross-domain path 'posedge crg_clk12' -> '<async>':
Info: curr total
Info:  1.4  1.4  Source $abc$53614$auto$blifparse.cc:492:parse_blif$53770_LC.O
Info:  5.8  7.2    Net $abc$53614$auto$ice40_ffinit.cc:141:execute$53446 budget -1.881000 ns (5,16) -> (16,24)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$53617_LC.I1
Info:  1.2  8.4  Source $abc$53614$auto$blifparse.cc:492:parse_blif$53617_LC.O
Info:  3.0 11.4    Net $abc$53614$n3959 budget 0.254000 ns (16,24) -> (20,24)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$53616_LC.I0
Info:  1.3 12.7  Source $abc$53614$auto$blifparse.cc:492:parse_blif$53616_LC.O
Info:  6.3 18.9    Net picorvspi_clk_pad_oe budget 19.521999 ns (20,24) -> (24,0)
Info:                Sink SB_IO_4.OUTPUT_ENABLE
Info: 3.9 ns logic, 15.0 ns routing

Info: Critical path report for cross-domain path 'posedge crg_clk12' -> 'posedge crg_clk48':
Info: curr total
Info:  1.4  1.4  Source $abc$53614$auto$blifparse.cc:492:parse_blif$54709_LC.O
Info:  6.2  7.6    Net usb_usb_core_tx_bitstuff_i_data budget -0.626000 ns (18,5) -> (20,28)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56486_LC.I1
Info:  1.2  8.8  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56486_LC.O
Info:  1.8 10.6    Net $abc$53614$n7366 budget 0.002000 ns (20,28) -> (20,27)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56485_LC.I0
Info:  1.3 11.9  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56485_LC.O
Info:  1.8 13.6    Net $abc$53614$auto$wreduce.cc:426:run$6862[1]_inv budget 0.002000 ns (20,27) -> (20,26)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56484_LC.I1
Info:  1.2 14.9  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56484_LC.O
Info:  1.8 16.6    Net $abc$53614$n7364 budget 0.928000 ns (20,26) -> (20,26)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56483_LC.I0
Info:  1.3 17.9  Source $abc$53614$auto$blifparse.cc:492:parse_blif$56483_LC.O
Info:  1.8 19.7    Net $abc$53614$procmux$5992.B_AND_S[9] budget 1.156000 ns (20,26) -> (20,25)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$56482_LC.I1
Info:  1.2 20.8  Setup $abc$53614$auto$blifparse.cc:492:parse_blif$56482_LC.I1
Info: 7.6 ns logic, 13.2 ns routing

Info: Critical path report for cross-domain path 'negedge crg_clk12' -> '<async>':
Info: curr total
Info:  1.4  1.4  Source $auto$simplemap.cc:420:simplemap_dff$10344_DFFLC.O
Info:  1.8  3.2    Net spimemio.xfer_io2_90 budget 11.909000 ns (23,2) -> (23,2)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$54641_LC.I2
Info:  1.2  4.4  Source $abc$53614$auto$blifparse.cc:492:parse_blif$54641_LC.O
Info:  1.8  6.1    Net $abc$53614$techmap\spimemio.$ternary$D:\Code\Fomu\foboot\hw\spimemio.v:168$1372_Y_inv budget 10.770000 ns (23,2) -> (22,2)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$54640_LC.I1
Info:  1.2  7.3  Source $abc$53614$auto$blifparse.cc:492:parse_blif$54640_LC.O
Info:  3.0 10.3    Net picorvspi_wp_pad_o budget 10.769000 ns (22,2) -> (22,0)
Info:                Sink SB_IO_6.D_OUT_0
Info:  0.2 10.5  Setup SB_IO_6.D_OUT_0
Info: 4.0 ns logic, 6.5 ns routing

Info: Critical path report for cross-domain path 'posedge crg_clk48' -> '<async>':
Info: curr total
Info:  1.4  1.4  Source $auto$simplemap.cc:420:simplemap_dff$15817_DFFLC.O
Info:  3.9  5.3    Net usb_iobuf_usb_tx_en budget 81.943001 ns (21,30) -> (13,31)
Info:                Sink SB_IO.OUTPUT_ENABLE
Info: 1.4 ns logic, 3.9 ns routing

Info: Critical path report for cross-domain path 'posedge crg_clk48' -> 'posedge crg_clk12':
Info: curr total
Info:  1.4  1.4  Source $auto$simplemap.cc:420:simplemap_dff$15817_DFFLC.O
Info:  3.2  4.5    Net usb_iobuf_usb_tx_en budget 9.595000 ns (21,30) -> (22,25)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$53713_LC.I0
Info:  1.3  5.8  Source $abc$53614$auto$blifparse.cc:492:parse_blif$53713_LC.O
Info:  1.8  7.6    Net $abc$53614$usb_usb_core_txstate_o_pkt_end budget 7.193000 ns (22,25) -> (22,25)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$54410_LC.I1
Info:  1.2  8.8  Source $abc$53614$auto$blifparse.cc:492:parse_blif$54410_LC.O
Info:  3.0 11.8    Net $abc$53614$n4854 budget 7.140000 ns (22,25) -> (20,23)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$54409_LC.I0
Info:  1.3 13.1  Source $abc$53614$auto$blifparse.cc:492:parse_blif$54409_LC.O
Info:  4.1 17.2    Net $abc$53614$n4853 budget 8.727000 ns (20,23) -> (12,28)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$55211_LC.I0
Info:  1.3 18.5  Source $abc$53614$auto$blifparse.cc:492:parse_blif$55211_LC.O
Info:  2.4 20.9    Net $abc$53614$n5825 budget 7.216000 ns (12,28) -> (12,30)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$55210_LC.I0
Info:  1.3 22.2  Source $abc$53614$auto$blifparse.cc:492:parse_blif$55210_LC.O
Info:  1.8 23.9    Net $abc$53614$usb_endpointin0_packet_trigger_inv budget 7.023000 ns (12,30) -> (12,30)
Info:                Sink $abc$53614$auto$blifparse.cc:492:parse_blif$55209_LC.I1
Info:  1.2 25.2  Source $abc$53614$auto$blifparse.cc:492:parse_blif$55209_LC.O
Info:  1.8 26.9    Net $abc$53614$or$top.v:3509$767_Y budget 7.287000 ns (12,30) -> (12,30)
Info:                Sink $auto$simplemap.cc:420:simplemap_dff$16640_DFFLC.I0
Info:  1.2 28.2  Setup $auto$simplemap.cc:420:simplemap_dff$16640_DFFLC.I0
Info: 10.2 ns logic, 17.9 ns routing

Info: Max frequency for clock     'clk48': 200.80 MHz (PASS at 48.00 MHz)
Info: Max frequency for clock 'crg_clk12': 12.58 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock 'crg_clk48': 49.27 MHz (PASS at 48.00 MHz)

Info: Max delay <async>           -> posedge crg_clk12: 16.39 ns
Info: Max delay <async>           -> posedge crg_clk48: 13.31 ns
Info: Max delay posedge crg_clk12 -> <async>          : 18.93 ns
Info: Max delay posedge crg_clk12 -> posedge crg_clk48: 20.84 ns
Info: Max delay negedge crg_clk12 -> <async>          : 10.51 ns
Info: Max delay posedge crg_clk48 -> <async>          : 5.28 ns
Info: Max delay posedge crg_clk48 -> posedge crg_clk12: 28.16 ns

Info: Slack histogram:
Info:  legend: * represents 23 endpoint(s)
Info:          + represents [1,23) endpoint(s)
Info: [    -4,   4006) |*+
Info: [  4006,   8016) |*+
Info: [  8016,  12026) |**+
Info: [ 12026,  16036) |***+
Info: [ 16036,  20046) |********+
Info: [ 20046,  24056) |*+
Info: [ 24056,  28066) |**+
Info: [ 28066,  32076) |***+
Info: [ 32076,  36086) |********+
Info: [ 36086,  40096) |***+
Info: [ 40096,  44106) |*****+
Info: [ 44106,  48116) |*****+
Info: [ 48116,  52126) |**********+
Info: [ 52126,  56136) |****************+
Info: [ 56136,  60146) |***************************+
Info: [ 60146,  64156) |*****************************************************+
Info: [ 64156,  68166) |*************************+
Info: [ 68166,  72176) |***********************+
Info: [ 72176,  76186) |******************************+
Info: [ 76186,  80196) |************************************************************
5 warnings, 0 errors

from vexriscv.

Dolu1990 commented on May 23, 2024

Right, there is 32 bits adder -> some stuff, 32 bits adder, and it was a mistake from my side, some combinatorial link leaking where it shoudln't have (Branch plugin target calculation was depending combinatorily from the success of the branch for STATIC and DYNAMIC prediction), you are using one of those right ?

It was fixed in the linux branch :D
63cd5f4 + 41ff87f

And then it also looked like one Quartus, the synthesis was reducing the area by doing some tricks which where greatly reducing the fmax by 40 %, fixed in :
13b774b

from vexriscv.

xobs commented on May 23, 2024

I use STATIC. Oddly, when I selected NONE, it didn't route at all.

Let me try those newer branches to see if it improves timing at all.

from vexriscv.

Dolu1990 commented on May 23, 2024

Maybe you will need a script which try new seeds untill it success ^^ ?

from vexriscv.

No trap generated for `divu` on core without divide about vexriscv HOT 13 CLOSED

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