Comments (1)
Personnaly, it isn't my plan to implement them, i'm very busy on other things, but i'm happy to merge PR :)
but I feel not as familiar with either Spinal or VexRiscv yet.
I understand the difficulty
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Related Issues (20)
- compiling verilog code in verilator by Verilator 4.216 2021-12-05 rev v4.216 HOT 1
- VexRiscvAxi4LinuxPlicClint not respecting the AXI protocol HOT 20
- Unsupported compressed instruction on VexRiscvAxi4LinuxPlicClint.scala HOT 3
- Where are the CLINT and PLIC described? HOT 5
- sbt fail: [error] error while loading <root>, Error accessing... scalactic_2.11-3.2.5.jar HOT 4
- Read speed: dcache width impact 32bit vs 64bit HOT 10
- MAC custom instruction implementation HOT 1
- Interface BSCAN2 with VexRiscv's JTAG HOT 3
- Assertion when tracing the elaboration issue HOT 5
- Adding FPU to AHBLite3 config file HOT 8
- Scratchpad memory with cached IBUS and DBUS? HOT 15
- Combinatorial loop with AhbLite3Decoder HOT 1
- Transfer data double times HOT 1
- Murax XIP compile issue HOT 11
- EmbeddedRiscvJtag synthesis issue HOT 7
- CPU exception signal HOT 3
- Regarding the result of dhrystone with TCM HOT 6
- debug HOT 1
- Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.) HOT 1
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