Two lint issues with the vexriscv.demo.GenFull configuration about vexriscv

[Dolu1990]

Hi,
The Verilog generator of SpinalHDL always assign the result of a shift operator into a variable to resize the result to the wanted size. (There is the list of all expression for which it do that : https://github.com/SpinalHDL/SpinalHDL/blob/dev/core/src/main/scala/spinal/core/internals/ComponentEmitterVerilog.scala#L1092)

So it isn't an issue, but a generator coding style ^^
Is that an issue in some cases ? Is that linting config standard ?
(I'm not used to linting tools)

[secworks]

Ok, if I look at the Verilog code I see:

On line 4422: assign zz_164 = (IBusCachedPlugin_fetchPc_output_payload >>> 2);
zz_164 is defined on row 2036 to "wire [29:0] zz_164;". So the assignment looses two bits.
But then on row 2064 the wire is used: "assign zz_330 = zz_164[9:0];" So we are actually only using the lowest 10 bits. No problem.

It is possible to disable these types of warnings, or build a list of known false errors to be ignored. In general I find that these warnings where the LHS and RHS widths of an assignment don't match usually points to some real issue. And esp if LHS width < RHS width you do loose info. So disabling lint checking assignment width mismatch should not be done. Generally.

I'm closing this issue.

BTW: We are looking at using VexRisc in the Cryptech Open HSM project. I'll be trying to use it at first as a SW controlled DMA/local master. So first core will be smallish, but include the debug port.
https://cryptech.is/