Murax debug on FPGA about vexriscv

[sebastien-riou]

I confirm nothing is wrong with Murax, I tried the "FT2232H_Mini_Module" with the exact same FPGA image and everything else, it works like a charm. The problem seems on JLink side or just a weird electrical connection problem, sorry about that.

[Dolu1990]

Hi,

Hmm that's is weird.
I never tried with that jtag key. Do you have another one ?
Can you also try to connect to the simulated Murax via the SpinalSim ? (sbt "test:runMain vexriscv.MuraxSim" + jtagtcp interface for openocd)

Those two things can help to diagnostic :)

[sebastien-riou]

Hi,

Thanks for the suggestion, I was not aware of SpinalSim.

SpinalSim works well.
the first relevant difference in the logs (as far as I can see) is this one:
SpinalSim:
Debug: 404 9045 gdb_server.c:3160 gdb_input_inner(): received packet: 'm80000080,40'
JLINK Hardware:
Debug: 2913 19593 gdb_server.c:3160 gdb_input_inner(): received packet: 'm80,40'

I ordered another jtag hardware

[Dolu1990]

Good :)
So, just to say, i'm using a FTDI2232H based breakout, i already tried with some others, as JtagKey, JtagKey2.
Some people also used raspberry pi by the past.

Let's me know how it go

[Dolu1990]

One thing. Today, i had to make one board working with the c232hm_ddhsl_0. And with that specific dongle, i had some issues. It was because of electrical reasons, bad impedance matching / crosstalk.
So what i finaly did, is adding a 380 ohm resistance between the FPGA pin and the dongle TCK pin (close to the FPGA) to filter that out. then it worked fine :)